IDT72V15165L15TFGI datasheet, PDF

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IDT72V15165L15TFGI: DescriptionFIFO, 4KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64; Categorystorage storage; File Size122KB，8 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT72V15165L15TFGI Overview

FIFO, 4KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64

IDT72V15165L15TFGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	10 X 10 MM, PLASTIC, STQFP-64
Contacts	64
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	10 ns
period time	15 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
memory density	65536 bi
memory width	16
Number of functions	1
Number of terminals	64
word count	4096 words
character code	4000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4KX16
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm

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3.3 VOLT MULTIMEDIA FIFO

256 x 16, 512 x 16,

1,024 x 16, 2,048 x 16,

and 4,096 x 16

IDT72V11165, IDT72V12165

IDT72V13165, IDT72V14165

IDT72V15165

FEATURES

•

DESCRIPTION

The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices

are First-In, First-Out (FIFO) memories with clocked read and write controls.

These FIFOs have 16-bit input and output ports. The input port is controlled

by a free-running clock (WCLK), and an input enable pin (WEN). Data is written

into the Multimedia FIFO on every clock when

WEN

is asserted. The output port

is controlled by another clock pin (RCLK) and another enable pin (REN). The

Read Clock (RCLK) can be tied to the Write Clock for single clock operation or

the two clocks can run asynchronous of one another for dual-clock operation.

An Output Enable pin (OE) is provided on the read port for three-state control

of the output.

These Multimedia FIFOs support three fixed flags: Empty Flag (EF), Full

Flag (FF), and Half Full Flag (HF).

256 x 16-bit organization array (IDT72V11165)

512 x 16-bit organization array (IDT72V12165)

1,024 x 16-bit organization array (IDT72V13165)

2,048 x 16-bit organization array (IDT72V14165)

4,096 x 16-bit organization array (IDT72V15165)

15 ns read/write cycle time

5V input tolerant

Independent Read and Write Clocks

Empty/Full and Half-Full flag capability

Output enable puts output data bus in high-impedance state

Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm

TQFP)

Industrial temperature range (–40°C to +85°C)

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN

WRITE

CONTROL

READ

CONTROL

RCLK

REN

FIFO ARRAY

- D

Data In

x16

- Q

Data Out

x16

RESET LOGIC

FLAG OUTPUTS

6359 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

2003

NOVEMBER 2003

DSC-6359/3

IDT72V15165L15TFGI Related Products

	IDT72V15165L15TFGI	IDT72V12165L15TFGI	IDT72V13165L15TFGI	IDT72V11165L15TFGI	IDT72V14165L15TFGI
Description	FIFO, 4KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64	FIFO, 512X16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64	FIFO, 1KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64	FIFO, 256X16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64	FIFO, 2KX16, 10ns, Synchronous, PQFP64, 10 X 10 MM, PLASTIC, STQFP-64
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP	QFP
package instruction	10 X 10 MM, PLASTIC, STQFP-64	LFQFP,	LFQFP,	LFQFP,	10 X 10 MM, PLASTIC, STQFP-64
Contacts	64	64	64	64	64
Reach Compliance Code	compli	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	10 ns	10 ns	10 ns	10 ns	10 ns
period time	15 ns	15 ns	15 ns	15 ns	15 ns
JESD-30 code	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64
JESD-609 code	e3	e3	e3	e3	e3
length	10 mm	10 mm	10 mm	10 mm	10 mm
memory density	65536 bi	8192 bit	16384 bit	4096 bit	32768 bit
memory width	16	16	16	16	16
Number of functions	1	1	1	1	1
Number of terminals	64	64	64	64	64
word count	4096 words	512 words	1024 words	256 words	2048 words
character code	4000	512	1000	256	2000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	4KX16	512X16	1KX16	256X16	2KX16
Exportable	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30
width	10 mm	10 mm	10 mm	10 mm	10 mm

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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