®
TDA7550/R TDA7551
TDA7552 TDA7553
DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND
AUDIO APPLICATIONS
PRODUCT PREVIEW
24-BIT, FIXED POINT, 50 MIPS DSP CORE
LARGE ON-BOARD PROGRAM ROM AND
DATA RAM (UP TO 16Kw ROM/RAM AND
16Kw RAM)
INTEGRATED STEREO A/D AND D/A, 16-BIT
SIGMA-DELTA
PROGRAMMABLE CODEC SAMPLE RATE
FROM 4 TO 48 kHz
ON-BOARD PLL FOR CORE CLOCK AND
CONVERTERS
MANAGEMENT
OF
EXTERNAL
FLASH/SRAM/DRAM MEMORY BANK
I
2
C OR SPI SERIAL INTERFACE FOR EX-
TERNAL CONTROL
80-PIN TQFP, 0.65 mm PITCH
AUTOMOTIVE GRADE (FROM -40° C to
+85°C)
DESCRIPTION
The TDA755X family is a high performances, fully
programmable 24-bit, 50 MIPS Digital Signal
BLOCK DIAGRAM
MULTIPLEXED BUS
TQFP80
Processor (DSP), designed to support several
speech and audio applications, as Automatic
Speech Recognition, Speech Synthesis, Speaker
Verification, Echo and Noise Cancellation. Soft-
ware for these applications is licenced by Lernout
& Hauspie and NCTI.
It offers an effective solution for this kind of appli-
cations because of the A/D and D/A converters
and the big amount of memory integrated on chip.
I
2
C/SPI
PORT
FLASH
INTERFACE
SAI
ROM/RAM
RAM
8
FLAGS
DSP
CORE
DAC
L
ANALOG OUT
R
L
ANALOG IN
R
ADC
PLL
D99AU1020A
September 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/12
TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553
APPLICATIONS
Real time digital speech and audio processing:
speech recognition, speech synthesis, speech
compression, echo cancelling, noise cancelling,
speaker verification.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DDP
V
D
, V
IN
T
op
T
stg
P
tot
Pads DC Supply Voltage
Digital or Analog Input Voltage
Operating Temperature Range
Storage Temperature Range
Total Maximum Power Dissipation
Parameter
Value
–0.3 to V
DD
+0.3
–0.3 to V
DDP
+0.3
–40 to +85
–55 to +150
Unit
V
V
°C
°C
mW
PIN CONNECTION
EMI_AD4
EMI_AD3
EMI_AD2
EMI_AD1
EMI_AD0
CLKOUT
REFCAP
CVDDA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
EMI_AD5
EMI_AD6
VDD
GND
EMI_AD7
EMI_A8
EMI_A7
EMI_A10
EMI_A11
EMI_A12
EMI_A13
EMI_A14
EMI_A15
VDD
GND
EMI_A16
EMI_A17
EMI_A18
EMI_A19
EMI_A20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
MOSI
GND
TEST3
LRCK
GND
SDO
GPIO1
VDD
SDI
SCK
VDD
GPIO0
GPIO5
EMI_A21
TEST1
TEST2
DWRN
DBCK
MISO
DBIN
TEST4
GPIO4
GPIO7
PGND
DRDN
PVCC
VREF
GND
VDD
XTO
ALE
XTI
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CGNDA
VINL
VINR
GND
VDD
VOUTL
VOUTR
CVDD
CGND
GPIO3
GPIO6
GPIO2
GND
VDD
SDA/SS
SCL/SCK
INTN
NRESET
DBRQN
DBOUT
TQFP80
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TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553
PIN FUNCTIONS
N.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Name
EMI_AD5
EMI_AD6
VDD
GND
EMI_AD7
EMI_A8
EMI_A9
EMI_A10
EMI_A11
EMI_A12
EMI_A13
EMI_A14
EMI_A15
VDD
GND
EMI_A16
EMI_A17
EMI_A18
EMI_A19
EMI_A20
EMI_A21
DWRN
TEST1
TEST2
MISO
MOSI
VDD
GND
TEST3
SDI
SCK
LRCK
VDD
GND
SDO
Type
I/O
I/O
I
I
I/O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
O
O
O
I
I
I/O
I/O
I
I
I
I
I/O
I/O
I
I
O
Description
EMI Multiplexed Address/Data Line 5. these pin acts as the EMI multiplexed
address and data line 5
EMI Multiplexed Address/Data Line 6. these pin acts as the EMI multiplexed
address and data line 6
Digital power supply
Ground
EMI Multiplexed Address/Data Line 7. these pin acts as the EMI multiplexed
address and data line 7
EMI Address Line 8. these pin acts as the EMI address line 8. The interface is
designed to address up to 4 Mbytes of External Flash, EPROM or SRAM.
EMI Address Line 9. these pin acts as the EMI address line 9.
EMI Address Line 10. these pin acts as the EMI address line 10.
EMI Address Line 11. these pin acts as the EMI address line 11.
EMI Address Line 12. these pin acts as the EMI address line 12.
EMI Address Line 13. these pin acts as the EMI address line 13.
EMI Address Line 14. these pin acts as the EMI address line 14.
EMI Address Line 15. these pin acts as the EMI address line 15.
Digital power supply
Ground
EMI Address Line 16. these pin acts as the EMI address line 16.
EMI Address Line 17. these pin acts as the EMI address line 17.
EMI Address Line 18. these pin acts as the EMI address line 18.
EMI Address Line 19. these pin acts as the EMI address line 19.
EMI Address Line 20. these pin acts as the EMI address line 20.
EMI Address Line 21. these pin acts as the EMI address line 21.
EMI Write Enable. This pin serves as the write enable for the EMI
Test 1. Used for test: set to LOW for normal operation
Test 2. Used for test: set to HIGH for normal operation
SPI Master Output Slave Input Serial Data. Serial Data Output for SPI type serial
Port when in SPI master Mode and Serial Data Input when in SPI Slave Mode
SPI Master Input Slave Output Serial Data. Serial Data Input for SPI type serial
Port when in SPI master Mode and Serial Data Output when in SPI Slave Mode
Digital Power Supply
Ground
Test 3. Used for test: set to LOW for normal operation
SAI Data Input
SAI Bit Clock
SAI Left/Right Clock
Digital power supply
Ground
SAI Data Output
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TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553
PIN FUNCTIONS
(continued)
N.
36
37
38
39
40
41
42
43
44
45
Name
GPIO1
GPIO0
GPIO5
DBCK
DBIN
DBOUT
DBRQN
NRESET
INTN
SCL/SCK
Type
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/O
I/O
46
SDA/SS
I/O
I
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
VDD
GND
GPIO2
GPIO6
GPIO3
CGND
CVDD
VOUTR
VOUTL
VDD
GND
VINR
VINL
CGNDA
TEST4
CVDDA
VREF
REFCAP
GPIO7
GPIO4
VDD
CLKOUT
I
I
I/O
I/O
I/O
I
I
O
O
I
I
I
I
I
O
I
O
O
I/O
I/O
I
O
General Purpose I/O
General Purpose I/O
General Purpose I/O
Debug port Bit Clock/Chip Status 1. The serial clock for the Debug Port is
provided. May also be used as GPIO9.
Debug port Serial Input/Chip Status 0. The serial data input for the Debug Port is
provided. May also be used as GPIO11.
Debug Port Serial Output. This pin is the serial Data output for the Debug port.
May also be used as GPIO10.
Debug Port Request Input. This pin is used to request Debug Mode operation to
Euterpe
System Reset. A low level applied to RESET input initializes the IC.
External interrupt line. When this line is asserted low the DSP may be interrupted.
I
2
C Serial Clock Line. Clock line for I
2
C bus. Schmitt trigger input.
SPI Bit Clock. If SPI interface is enabled, it behaves as SPI bit clock.
I
2
C Serial Data Line. Data line for I
2
C bus. Schmitt trigger input.
SPI Slave Select. If SPI interface is enabled, it behaves as Slave select line for
SPI bus.
Digital Power Supply
Ground
General Purpose I/O
General Purpose I/O
General Purpose I/O
Ground for the internal CODEC cell
Power Supply for the internal CODEC cell
Single-ended right channel analogue output from DAC
Single-ended left channel analogue output from DAC
Digital power supply
Ground
Single-ended right channel analogue input to ADC
Single-ended left channel analogue input to ADC
Ground for the internal CODEC cell
Connect a 22K pull-down resistor
Power Supply for the internal CODEC cell
Voltage Reference from the CODEC cell
Voltage Reference Capacitor Bypass
General Purpose I/O
General Purpose I/O
Digital power supply
Clock Output. Output Clock divided down from PLL
Description
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TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553
PIN FUNCTIONS
(continued)
N.
69
70
71
72
73
74
75
76
77
78
79
80
Name
XTI
PGND
PVCC
XTO
ALE
GND
DRDN
EMI_AD0
EMI_AD1
EMI_AD2
EMI_AD3
EMI_AD4
Type
I
O
I
O
O
I
O
I/O
I/O
I/O
I/O
I/O
Description
Crystal Oscillator Input. Crystal Oscillator Input drive
PLL Ground Input. Ground connection for Oscillator circuit
PLL Power Supply Positive. Supply for PLL Clock Oscillator
Crystal Oscillator Output. Crystal Oscillator Output drive
EMI Address Latch Enable. This pin acts as the EMI Address Latch Enable for the
External Memory Interface
Ground
EMI Read Enable. This pin serves as the read enable for the EMI
EMI Multiplexed Address/Data Line 0. these pin acts as the EMI multiplexed
address and data line 0
EMI Multiplexed Address/Data Line 1. these pin acts as the EMI multiplexed
address and data line 1
EMI Multiplexed Address/Data Line 2. these pin acts as the EMI multiplexed
address and data line 2
EMI Multiplexed Address/Data Line 3. these pin acts as the EMI multiplexed
address and data line 3
EMI Multiplexed Address/Data Line 4. these pin acts as the EMI multiplexed
address and data line 4
RECOMMENDED DC OPERATING CONDITIONS
Symbol
V
DD
T
J
Parameter
Power Supply Volrage Range
Operating Junction Temp.
Test Condition
Min.
3
–40
Typ.
3.3
Max.
3.6
125
Unit
V
°C
5/12
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