MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC145745
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V.21/V.23 Telemeter Modem
The MC145745 is a selectable modem chip compatible with ITU V.21
(300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex
asynchronous). The built–in differential line driver has the capability of driving
0 dBm into a 600
Ω
load with a 5 V single power supply. This device also
includes a DTMF generator, DTMF receiver, call–progress tone detector,
answer tone generator, and a receive timing control circuit.
Besides having a clock generator with a crystal oscillator connected to it, the
device has a divider circuit to which input of a double frequency clock is possible
from external sources, such as from a microcontroller unit (MCU). The serial
control port (SCP) permits the MCU to access internal registers for exercising
the built–in features.
A low consumption device, the MC145745 integrates various functions in a
small package. This modem IC is best suited for telemeter and other
applications of this type.
•
•
•
•
•
•
•
•
•
Conforms to ITU V.21 and V.23 Recommendations
DTMF Generator and Receiver for all 16 Standard Digits
Capable of Driving 0 dBm into a 600
Ω
Load (VCC = 5 V)
Automatic Gain Control (AGC) Amplifier for the DTMF Receiver
Call–Progress Tone Detector
Four–Wire Serial Data Interface (SCP)
Programmable Transmission and Carrier Detection Levels
FSK/DTMF Analog Loopback Self–Test Function
Crystal Oscillator (3.579545 MHz) and Half Divider Circuit (7.159090 MHz)
for External Inputs
•
Operates in the Voltage Range of 3.3 – 5.5 V
•
Power Down Mode (ICC < 1
µA)
28
1
FW SUFFIX
SOIC
CASE 751M
ORDERING INFORMATION
MC145745FW
SOIC
PIN ASSIGNMENT
GND
Vref
CDA
TLA
TEST 1
RxD
TxD
CD
CLKO
X1
X2
ECLK
PB0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
RxA
TxA1
TxA2
TEST 2
SCPEN
SCPCLK
SCP Rx
SCP Tx
RESET
PB3
PB2
PB1
VCC
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 0
7/96
©
Motorola, Inc. 1996
MOTOROLA
MC145745
1
BLOCK DIAGRAM
RxA
Rx AMP
AND AGC
CONTROL
LOOPBACK
PATH
SMOOTHING
FILTER
AND
Tx GAIN
CONTROL
1/2
4
ANTI–ALIAS
AND
LOW–PASS
FILTER
TONE
GENERATOR
DTMF
RECEIVER
CPT
DETECTOR
FSK
CARRIER
DETECTOR
FSK V.21
MODEM
FSK V.23
MODEM
TIMING
CONTROL
CIRCUIT
PB0 – PB3
CDA
Vref
CD
TxA2
TxA1
–
+
TxD
RxD
CLKO
CLOCK
GENERATOR
RESET
X1
X2
ECLK
TLA
VCC
GND
SCP Tx
SCP Rx SCPEN
SCPCLK
MC145745
2
MOTOROLA
PIN DESCRIPTIONS
Pin
Location
1, 14
2
3
Symbol
GND
Vref
CDA
Type
—
—
—
Description
Ground — These are the ground pins of the digital and the analog circuits. The 0 V potential of the
device is determined by the input voltage at these pins.
Reference Analog Ground — This pin provides the analog ground voltage VCC/2, which is regulated
internally. This pin should be decoupled to GND with 0.1
µF
and 100
µF
capacitors.
Carrier Detect Level Adjustment — The detection level for FSK/call–progress tone is determined
according to the voltage at this pin. When VCC = 5 V and the carrier detection level bit (BR3:b1) of the
SCP register is 0, or when VCC = 3.6 V and (BR3:b1) is 1, the CDA voltage is set to 1.25 V by the
internal divider.
This voltage sets the detection levels at ON to OFF: – 44 dBm (typ) and OFF to ON: – 47 dBm (typ).
This high impedance pin should be decoupled to GND with a 0.1
µF
capacitor.
The carrier detection level is proportional to the terminal voltage at this pin.
An external voltage may be applied to this pin to adjust the carrier detect threshold. The following
equations may be used to find the CDA voltage requirements for a given threshold voltage.
VCDA = 256 x Von
VCDA = 362 x Voff
Transmit Level Adjustment — This pin is used to adjust the transmit carrier level which is determined
by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when
this pin is shorted to GND (RTLA = 0).
Test Pins 1 and 2 — These test pins are for manufacturer’s use only. These pins should be left open in
normal operation.
Receive Data Output — This pin is the receive data output. When the device is in the FSK mode, logic
high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic
low indicates that the space carrier frequency has been received.
Transmit Data Input — This pin is the transmit data input. When the device is in the FSK mode, logic
high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the
space frequency.
Carrier Detect Output — This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is
received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level
to avoid erroneous output of received data caused by line noise.
Clock Output — This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device
such as the MC74HC04.
Crystal Oscillator Circuit Output — A 3.579545 MHz
±
0.1% crystal oscillator is tied to this pin with the
other end connected to X2.
Crystal Oscillator Circuit Input — A 3.579545 MHz
±
0.1% crystal oscillator is tied to this pin with the
other end connected to X1. X2 may be driven directly from an appropriate external clock source.
External Clock Input — ECLK is the input of double frequency, 7.159090 MHz
±
0.1%, of the reference
clock. This pin must be connected to GND when not in use.
DTMF Receive Data Parallel Output 0 (LSB) — Pins 13, 16, 17, and 18 are the DTMF receive data
parallel output occurring together with the CD (Pin 8) data valid output. The outputs of these pins are
valid as long as the CD pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and
these pins are in high impedance.
Positive Power Supply — These are the power supply pins for the digital and the analog circuits.
These pins should be decoupled to GND with 0.1
µF
and 100
µF
capacitors.
DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) — These pins are the DTMF receiver data
parallel outputs. See pin 13 for more details
details.
outputs
Reset — A high to low trigger pulse applied to this pin sets all the registers in the default state. It
should remain at high during normal operations.
SCP Output Transmit — Refer to
Serial Control Port (SCP Interface)
for additional information.
SCP Receive Input — Refer to
Serial Control Port (SCP Interface)
for additional information.
SCP Clock — Refer to
Serial Control Port (SCP Interface)
for additional information.
SCP Enable — Refer to
Serial Control Port (SCP Interface)
for additional information.
4
TLA
—
5, 24
6
TEST 1,
TEST 2
RxD
I/O
O
7
TxD
I
8
CD
O
9
10
11
12
13
CLKO
X1
X2
ECLK
PB0
O
O
I
I
O
15, 28
16, 17, 18
19
20
21
22
23
VCC
PB1, PB2,
PB3
RESET
SCP Tx
SCP Rx
SCPCLK
SCPEN
—
O
I
O
I
I
I
MOTOROLA
MC145745
3
PIN DESCRIPTIONS (continued)
Pin
Location
25
Symbol
TxA2
Type
O
Description
Transmit Buffer Output 2 (Inverting) — This pin is the inverting output of the line driver. When VCC =
5 V, + 7 dBm (typ), differential output voltage (VTxA1 – VTxA2), can be obtained with a load of 1.2 kΩ
between pins TxA1 and TxA2. In typical applications, the output level on the telephone line will be half
of the differential output (refer to
Application Circuit).
Transmit Buffer Output 1 (Non–Inverting) — This pin is the non–inverting output of the line driver.
Refer to TxA2.
Receive Signal Input — This pin is the analog signal input which has 500 kΩ input resistance (typ).
26
27
TxA1
RxA
O
I
ABSOLUTE MAXIMUM RATINGS
Rating
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Power Dissipation
Storage Temperature Range
Symbol
VCC
Vin
Vout
Iin
Iout
PD
Tstg
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
±
20
±
25
500
– 65 to + 150
Unit
V
V
V
mA
mA
mW
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields. However, it is advised
that normal precautions be taken to avoid ap-
plications of any voltage higher than maximum
rated voltages to this high impedance circuit. For
proper operation, it is recommended that Vin and
Vout be constrained to the range GND (Vin or
Vout)
VCC.
Reliability of operation is enhanced if unused
logic inputs are tied to an appropriate logic volt-
age level (e.g., either GND or VCC).
v
v
RECOMMENDED OPERATIONAL CONDITIONS
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Crystal Oscillation Frequency
External Input Frequency (ECLK)
Operating Temperature Range
TA
Symbol
VCC
Vin
Vout
fosc
Min
3.3
0
0
—
—
– 30
Typ
5.0
—
—
3.579545
7.15909
25
Max
5.5
VCC
VCC
—
—
+ 85
°C
Unit
V
V
V
MHz
DC ELECTRICAL CHARACTERISTICS
(VCC = + 3.3 to + 5.5 V, TA = – 30 to + 85°C)
Characteristic
Input Voltage
(TxD, ECLK, RESET,
(
SCP R SCPCLK
Rx, SCPCLK,
SCPEN)
Output Voltage
(RxD, CD, CLKO
(RxD CD CLKO,
PB0–3, SCP Tx)
High Level
Low Level
High Level
Low Level
Symbol
VIH
VIL
VOH
VOL
Vin = VIH or VIL, Iout = 20
µA
Vin = VIH or VIL
Iout = 20
µA
Iout = 2 mA
Vin = VCC or GND
Conditions
Min
0.7 x VCC
—
VCC – 0.1
—
—
—
Typ
—
—
VCC – 0.01
0.01
—
±
1.0
Max
—
1.1
—
0.1
0.4
±
10.0
µA
Unit
V
Input Leakage Current
(TxD, ECLK, RESET, SCP Rx,
SCPCLK, SCPEN)
Quiescent Supply
Current
VCC = 5 V
Iin
ICC
FSK Mode, RTLA = 0
TxA1 and TxA2 open
DTMF Receive Mode, no input
—
—
—
—
—
—
7
9
6
8
—
—
—
—
—
—
500
1.0
mA
VCC = 3.6 V
ICC
FSK Mode, RTLA = 0
TxA1 and TxA2 open
DTMF Receive Mode, no input
Power–Down Supply Current
ICC
Power–Down Mode 1
Power–Down Mode 2
µA
µA
MC145745
4
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(VCC = + 3.6 V
±
0.3 V, TA = – 30 to + 85
_
C)
TRANSMIT CARRIER CHARACTERISTICS
Characteristic
V.21 Carrier Frequency
Originate Mode
V.21 Carrier Frequency
Answer Mode
V.23 Carrier Frequency
Mark “1”
Space “0”
Mark “1”
Space “0”
Mark “1”
Space “0”
Transmit Carrier Level
Secondary Harmonic Level
Out–of–Band Level
Symbol
f1M
f1S
f2M
f2S
f1M
f1S
VO
V2h
VOE
Transmit Attenuator = 0 dB
RTLA = 0 RL = 1 2 kΩ
0,
1.2
VTxA1 – VTxA2
Conditions
Oscillation Frequency:
3.579545
3 579545 MHz (X2)
or 7.159090 MHz (ECLK)
Min
974
1174
1644
1844
1294
2094
—
—
Typ
980
1180
1650
1850
1300
2100
4
– 40
Refer to Figure 1
Max
986
1186
1656
1856
1306
2106
—
—
dBm
dB
dBm
Unit
Hz
TRANSMIT ATTENUATOR CHARACTERISTICS
Characteristic
Attenuation Range
Attenuator Accuracy
1 – 5 dB
6 – 9 dB
10 – 15 dB
Symbol
Conditions
Min
0
– 0.5
–1
– 1.7
Typ
—
—
—
—
Max
15
0.5
1
1
Unit
dB
dB
RECEIVER CHARACTERISTICS
(Includes Hybrid, Demodulator, and Carrier Detector)
Characteristic
Input Resistance
Receive Carrier Amplitude
Carrier Detection
Threshold
OFF to ON
ON to OFF
Symbol
RIRX
VIRX
VCDON
VCDOFF
HYS
TCDON
CD1 = 0, CD0 = 0, CD Pin
CD1 = 0, CD0 = 1, CD Pin
CD1 = 1, CD0 = 0, CD Pin
CD1 = 1, CD0 = 1, CD Pin
ON to OFF
TCDOFF
CD1 = 0, CD0 = 0, CD Pin
CD1 = 0, CD0 = 1, CD Pin
CD1 = 1, CD0 = 0, CD Pin
CD1 = 1, CD0 = 1, CD Pin
CDA = 1.25 V
fi = 1.0 kHz
in 1 0
BR3 (b1) = 1
Conditions
Min
50
– 48
—
—
2
—
—
—
—
—
—
—
—
Typ
500
—
– 44
– 47
—
450
15
15
75
30
30
15
10
Max
—
– 12
—
—
—
—
—
—
—
—
—
—
—
dB
ms
Unit
kΩ
dBm
dBm
Hysteresis (VCDON – VCDOFF)
Carrier Detection Timing
OFF to ON
CPTD CHARACTERISTICS
Characteristic
BPF Center Frequency
BPF Pass–Band Lower Cut–Off
Frequency
BPF Pass–Band Upper Cut–Off
Frequency
CPT Detection Level
VTD ON
VTD OFF
CPT Detection Timing
TTD ON
TTD OFF
Symbol
fc
fi
fh
VTDON
VTDOFF
TTDON
TTDOFF
– 3 dB
– 3 dB
CDA = 1.25 V
fi = 400 Hz
in
BR3 (b1) = 1
Conditions
Min
—
—
—
—
—
—
—
Typ
400
330
470
– 44
– 47
10
25
Max
—
—
—
—
—
—
—
ms
Unit
Hz
Hz
Hz
dBm
MOTOROLA
MC145745
5
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