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PDM31564SA20SO

Description
Standard SRAM, 512KX8, 20ns, CMOS, PDSO44
Categorystorage    storage   
File Size365KB,9 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM31564SA20SO Overview

Standard SRAM, 512KX8, 20ns, CMOS, PDSO44

PDM31564SA20SO Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerParadigm Technology Inc
package instructionSOJ, SOJ44,.44
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J44
JESD-609 codee0
memory density4194304 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals44
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ44,.44
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.01 A
Minimum standby current3 V
Maximum slew rate0.185 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
PRELIMINARY
PDM31564
PDM31564
256K x 16 CMOS
3.3V Static RAM
Features
n
Description
The PDM31564 is a high-performance CMOS static
RAM organized as 262,144 x 16 bits. The PDM31564
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31564 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31564 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP package for high-density
surface assembly and is suitable for use in high-
speed applications requiring high-speed storage.
1
2
3
4
5
6
n
n
n
n
n
n
n
n
High-speed access times
- Com’l: 8, 10, 12, 15, and 20 ns
- Ind: 12, 15, and 20 ns
Low power operation (typical)
- PDM31564SA
Active: 300 mW
Standby: 25mW
High-density 256K x 16 architecture
3.3V (±0.3V) power supply
Fully static operation
TTL-compatible inputs and outputs
Output buffer controls: OE
Data byte controls: LB, UB
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
Row Address
Buffer
Row Decoder
Vcc
Vss
7
Memory
Cell
Array
256 x
x
128 x 32
512 256 x
A8 - A0
A7-A0
8
9
10
11
I/O15-I/O0
Data
Input/
Output
Buffer
Sense Amp
Column
Decoder
WE
OE
UB
LB
CE
Control
Logic
Clock
Generator
Column
Address
Buffer
12
A17 - A9
A15-A8
Rev. 1.2 - 3/31/98
1
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