Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Operational environment:
- Total dose: 50 krads(Si)
- SEL Immune 110 MeV-cm
2
/mg
- SEU LET
TH
(0.25) = 52 cm
2
MeV
- Saturated Cross Section 2.8E-8 cm
2
/bit
-<1.1E-9 errors/bit-day, Adams 90% worst case
environment geosynchronous orbit
Packaging:
- 36-lead ceramic flatpack (3.831 grams)
Standard Microcircuit Drawing 5962-00536
- QML Q and V compliant part
INTRODUCTION
The UT9Q512E RadTol product is a high-performance CMOS
static RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E), an
active LOW Output Enable (G), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable (E)
input LOW and Write Enable (W) inputs LOW. Data on the eight
I/O pins (DQ
0
through DQ
7
) is then written into the location
specified on the address pins (A
0
through A
18
). Reading from
the device is accomplished by taking Chip Enable (E) and
Output Enable (G) LOW while forcing Write Enable (W) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (DQ
0
through DQ
7
) are placed in a
high impedance state when the device is deselected (E HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOW and W LOW).
Clk. Gen.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Pre-Charge Circuit
Row Select
Memory Array
1024 Rows
512x8 Columns
I/O Circuit
Column Select
Data
Control
CLK
Gen.
A10
A11
A12
A13
A14
A15
A16
A17
A18
DQ
0
- DQ
7
E
W
G
Figure 1. UT9Q512E SRAM Block Diagram
1
DEVICE OPERATION
A0
A1
A2
A3
A4
E
DQ0
DQ1
V
DD
V
SS
DQ2
DQ3
W
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
G
DQ7
DQ6
V
SS
V
DD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
The UT9Q512E has three control inputs called Chip Enable (E),
Write Enable (W), and Output Enable (G); 19 address inputs,
A(18:0); and eight bidirectional data lines, DQ(7:0). E controls
device selection, active, and standby modes. Asserting E enables
the device, causes I
DD
to rise to its active value, and decodes the
19 address inputs to select one of 524,288 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
1
X
1
0
W
X
0
1
1
E
1
0
0
0
I/O Mode
3-state
Data in
3-state
Data out
Mode
Standby
Write
Read
2
Read
Figure 2. UT9Q512E 20ns SRAM Pinout (36)
PIN NAMES
A(18:0)
DQ(7:0)
E
W
G
V
DD
V
SS
Address
Data Input/Output
Chip Enable
Write Enable
Output Enable
Power
Ground
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than V
IH
(min) and E less than V
IL
(max) defines a read cycle. Read access time is measured from
the latter of Chip Enable, Output Enable, or valid address to
valid data output.
SRAM Read Cycle 1, the Address Access in figure 4a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as Chip
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t
AVAV
).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 4b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t
ETQV
is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 4c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
t
GLQV
unless t
AVQV
or t
ETQV
have not been satisfied.
2
WRITE CYCLE
A combination of W less than V
IL
(max) and E less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than V
IH
(min), or when W is less
than V
IL
(max).
Write Cycle 1, the Write Enable - Controlled Access in figure
5a, is defined by a write terminated by W going high, with E
still active. The write pulse width is defined by t
WLWH
when the
write is initiated by W, and by t
ETWH
when the write is initiated
by E. Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait t
WLQZ
before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable - Controlled Access in figure
5b, is defined by a write terminated by E going inactive. The
write pulse width is defined by t
WLEF
when the write is initiated
by W, and by t
ETEF
when the write is initiated by the E going
active. For the W initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait t
WLQZ
before applying data to the eight bidirectional
pins DQ(7:0) to avoid bus contention.
OPERATIONAL ENVIRONMENT
Table 2. Operational Environment
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
50
<1.1E-9
krad(Si)
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Adam’s 0% worst case environment, Geosynchronous orbit, 100 mils of
Aluminum.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.5 to 7.0V
-0.5 to 7.0V
-65 to +150°C
1.0W
+150°C
10°C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
4.5 to 5.5V
(C) screening: -55°C to +125°C
(W) screening: -40°C to +125°C
0V to V
DD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-55°C to +125°C for (C) screening and -40
o
C to +125
o
C for (W) screening (V
DD
= 5.0V + 10%)
SYMBOL
V
IH
V
IL
V
OL1
V
OL2
V
OH1
V
OH2
C
IN1
C
IO1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
(TTL)
(TTL)
I
OL
= 8mA, V
DD
=4.5V (TTL)
I
OL
= 200μA,V
DD
=4.5V (CMOS)
I
OH
= -4mA,V
DD
=4.5V (TTL)
I
OH
= -200μA,V
DD
=4.5V (CMOS)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD
and V
SS,
V
DD
= V
DD
(max)
V
O
= V
DD
and V
SS
V
DD
= V
DD
(max)
G = V
DD
(max)
V
DD
= V
DD
(max), V
O
= V
DD
V
DD
= V
DD
(max), V
O
= 0V
I
DD
(OP)
4
Supply current operating
@ 1MHz
Inputs: V
IL
= 0.8V,
V
IH
= 2.0V
I
OUT
= 0mA
V
DD
= V
DD
(max)
Inputs: V
IL
= 0.8V,
V
IH
= 2.0V
I
OUT
= 0mA
V
DD
= V
DD
(max)
Inputs: V
IL
= V
SS
I
OUT
= 0mA
E = V
DD
- 0.5
V
DD
= V
DD
(max)
V
IH
= V
DD
- 0.5V
-55°C, -40°C, 25°C
125°C
50
mA
-2
-2
2.4
3.2
10
12
2
2
CONDITION
MIN
2
0.8
0.4
0.05
MAX
UNIT
V
V
V
V
V
V
pF
pF
μA
μA
I
OS2, 3
Short-circuit output current
-90
90
mA
I
DD
(OP)
4
Supply current operating
@50MHz
76
mA
I
DD
(SB)
Supply current standby
@0MHz
10
45
mA
mA
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
1 I went on a business trip with my colleagues. The local colleagues were very hospitable. That night, we had a banquet in a private room of a special hotel. After more than a dozen men and women sa...
Live Topic: How to Solve Precision Timing Challenges in ADAS Systems
Live broadcast time: 10:30-11:30 am, June 21, 2022 (Tuesday)Watch Livebrief introduction
Autonomous vehicles require extremely accu...
[size=4]Guide to Modern Electronic Process Technology[/size] [size=4][/size] [size=4] [/size][b] [url=https://download.eeworld.com.cn/detail/qwqwqw2088/590192]Guide to Modern Electronic Process Techno...
The serial communication I am doing now is sending data to the hardware, the hardware responds, and then returns the response information data, but the data sent back is sometimes one line, sometimes ...
With the promotion of the construction of intelligent communities in the country, anti-theft systems have become essential equipment for intelligent communities. Especially in recent years, the urg...[Details]
1. Overview
Will passive devices
produce nonlinear intermodulation distortion? The answer is yes! Although there is no systematic theoretical analysis, it has been found in engineerin...[Details]
1. Introduction
This design was made for participating in an electronic design competition. It effectively solved the problem of the operation and control of an electric car on a seesaw. The s...[Details]
With the advent of increasingly powerful processors, image sensors, memory, and other semiconductor devices, as well as the algorithms that enable them, computer vision can be implemented in a wide...[Details]
In recent years, lighting has become an important area that countries around the world are targeting to promote energy conservation and environmental protection. According to statistics, about 20% ...[Details]
On the afternoon of July 10, Beijing time, Taiwan's largest chip designer MediaTek expects its smartphone chip shipments to grow by double digits in the third quarter of this year, and the company is ...[Details]
We know that the inverter consists of two parts: the main circuit and the control circuit. Due to the nonlinearity of the main circuit (switching action), the inverter itself is a source of harmoni...[Details]
In today's body control module (BCM) designs, savvy engineers are moving away from electromechanical relays whenever possible. Their next step is to eliminate fuses. But is eliminating fuses a nece...[Details]
As people's requirements for safety and comfort in the process of driving cars continue to increase, automotive radars are widely used in the car's adaptive cruise system, collision avoidance syste...[Details]
Abstract: The output of high-range acceleration sensor is less than 10 mV under the excitation of small signal. The noise of traditional test system may cover such small voltage signal, so that hig...[Details]
Since AC mains power may experience power outages, voltage sags and surges, continuous undervoltage and overvoltage, and frequency fluctuations during supply, these factors will affect the continuous ...[Details]
Currently, each country is developing its own USB interface
charging specifications
, which leads to a major problem that a USB interface
charging
device manufactured in one country...[Details]
summary
This article will briefly analyze the success and shortcomings of high-frequency DC-DC switching power supplies in the process of miniaturization (the second basic goal), and propose m...[Details]
The automotive power electronics market has grown rapidly as comfort and active safety features become more common. As traditional mechanical functions shift to electronic applications, the demand ...[Details]
introduction
The core features of mobile value-added service products are mobility, immediacy and personalization. Mobile value-added services are a new service mode that is rapidly developing...[Details]
Talking
京公网安备 11010802033920号
EEWORLD
