SMQR-67024L-35MH datasheet, PDF

SMQR-67024L-35MH: DescriptionMulti-Port SRAM, 4KX16, 35ns, CMOS, CQCC84; Categorystorage storage; File Size727KB，22 Pages; ManufacturerMatra MHS

Download Datasheet Parametric View All

SMQR-67024L-35MH Overview

Multi-Port SRAM, 4KX16, 35ns, CMOS, CQCC84

Parameter Name	Attribute value
Maker	Matra MHS
package instruction	,
Reach Compliance Code	unknow
ECCN code	3A001.A.2.C
Maximum access time	35 ns
Other features	INTERRUPT FLAG; ARBITER; SEMAPHORE
JESD-30 code	S-GQCC-J84
memory density	65536 bi
Memory IC Type	MULTI-PORT SRAM
memory width	16
Number of functions	1
Number of ports	2
Number of terminals	84
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	4KX16
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, GLASS-SEALED
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Minimum standby current	2 V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	J BEND
Terminal location	QUAD

Memory performance test based on BeagleBone: Author: chenzhufly QQ: 36886052 (Please indicate the source when reprinting) I haven't posted anything for a long time. I've been quite busy recently, but the progress is still good. I just haven't re...; chenzhufly DSP and ARM Processors

WEBENCH is used in automotive electronics design tools!: [align=left]By Surinder Singh[/color][/url][/align][align=left]When I flew into Fort Myer, Florida, last week, there was a display of classic Ford cars. The nearly 100-year-old Fords on display in the...; qwqwqw2088 Analogue and Mixed Signal

SOCFPGA underlying FPGA data acquisition architecture diagram: [i=s]This post was last edited by yupc123 on 2016-1-18 10:14[/i] SOCFPGA underlying fpga data acquisition architecture diagram, integrating frequency division, level trigger, edge trigger and other fu...; yupc123 FPGA/CPLD

Dear bachelors, do you cook your dinner yourself or eat out?: As the title says, I graduated from college this year and started working. I always felt that eating was a big problem, and it was more comfortable to cook for myself, but after a while I found that i...; lingking Talking

A binary to BCD conversion problem, please analyze it: Convert a binary to BCD code, using the data captured by the logic analyzer, the maximum input data is 189975, and after adding 60000, the maximum is 249975. Usually, this data is constantly changing,...; eeleader FPGA/CPLD

Some questions about using AT to operate GSM Modem to send SMS: When I use AT commands to interact with the modem, I am always worried that if I receive a new SMS status report during this period, will the received data be discarded because the modem needs to resp...; boao Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components