Features
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Advanced, High-speed, Electrically-erasable Programmable Logic Device
– Superset of 22V10
– Enhanced Logic Flexibility
– Backward Compatible with ATV750B/BL and ATV750/L
Low-power Edge-sensing “L” Option with 1 mA Standby Current
D- or T-type Flip-flop
Product Term or Direct Input Pin Clocking for Flip-flop
7.5 ns Maximum Pin-to-pin Delay with 5V Operation
Highest Density Programmable Logic Available in 24-pin and 28-pin Packages
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
Programmable Pin-keeper Circuits
Dual-in-line and Surface Mount Package in Standard Pinouts
Full Military, Commercial and Industrial Temperature Ranges
20-year Data Retention
2000V ESD Protection
1000 Erase/Write Cycles
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
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High-speed
Complex
Programmable
Logic Device
ATF750C
ATF750CL
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1. Block Diagram
(OE PRODUCT TERMS)
12
INPUT
PINS
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
4 TO 8
PRODUCT
TERMS
LOGIC
OPTION
(UP T0 20
FLIP-FLOPS)
OUTPUT
OPTION
10
I/O
PINS
(CLOCK PIN)
0776L–PLD–11/08
2. Pin Configurations
Pin
CLK
IN
I/O
GND
VCC
Function
Clock
Logic Inputs
Bi-directional Buffers
Ground
+5V Supply
2.1
DIP/SOIC/TSSOP
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
2.2
PLCC/LCC
IN
IN
CLK/IN
VCC
(1)
VCC
I/O
I/O
4
3
2
1
28
27
26
Note:
For PLCC, pins 1, 8, 15, and 22 can be left uncon-
nected. For superior performance, connect VCC to pin 1
and GND to pins 8, 15, and 22.
3. Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices.
Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform predictable delays guarantee
fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-eras-
able) complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-
erasable technology.
Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as
inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or
T-type. Each flip-flop output is fed back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms available. There are two sum terms per output, providing
added flexibility. A variable format is used to assign between four to eight product terms per sum
term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20
sum terms and flip-flops, complex state machines are easily implemented with logic to spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop
may also be individually configured to have direct input pin controlled clocking. Each output has
its own enable product term. One product term provides a common synchronous preset for all
flip-flops. Register preload functions are provided to simplify testing. All registers automatically
reset upon power-up.
The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL provides the
optimum low-power CPLD solution. This device significantly reduces total system power,
thereby allowing battery-powered operations.
2
ATF750C(L)
0776L–PLD–11/08
IN
IN
GND
GND
(1)
IN
I/O
I/O
12
13
14
15
16
17
18
IN
IN
IN
GND
(1)
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
GND
(1)
I/O
I/O
I/O
ATF750C(L)
4. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
CC
+ 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
5. DC and AC Operating Conditions
All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to
be either 2.7V to
3.6V,
5V ±5% or 5V ±10%.
Commercial
-7.5, -10, -15
0°C - 70°C
5V ± 5%
Industrial
-10, -15
-40°C - +85°C
5V ± 10%
5V Operation
Operating Temperature (Ambient)
V
CC
Power Supply
Military
-55°C - +125°C
(case)
5V ± 10%
3
0776L–PLD–11/08
6. Logic Options
Combinatorial Output
Combined Terms
Separate Terms
Registered Output
Combined Terms
Separate Terms
7. Clock Mux
CKMUX
CKi
CLOCK
PRODUCT
TERM
CLK
PIN
TO
LOGIC
CELL
SELECT
8. Output Options
4
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
9. Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750C(L) have programmable “pin-keeper” circuits. If activated,
when any pin is driven high or low and then subsequently left floating, it will stay at that previous
high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels,
which causes unnecessary power consumption and system noise. The keeper circuits eliminate
the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the software compiler table for more
details. Once the pin-keeper circuits are disabled, normal termination procedures are required
for unused inputs and I/Os.
10. Input Diagram
V
CC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
11. I/O Diagram
V
CC
OE
DATA
I/O
V
CC
100K
PROGRAMMABLE
OPTION
5
0776L–PLD–11/08
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