80525PY550512 datasheet, PDF - EEWORLD Datasheet

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80525PY550512: DescriptionMicroprocessor, CMOS; CategoryThe embedded processor and controller Microcontrollers and processors; File Size881KB，108 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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80525PY550512 Overview

Microprocessor, CMOS

80525PY550512 Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknow
ECCN code	3A001.A.3
Address bus width	36
boundary scan	YES
maximum clock frequency	550 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	R-XXMA-X
low power mode	YES
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
Nominal supply voltage	2 V
surface mount	NO
technology	CMOS
Terminal form	UNSPECIFIED
Terminal location	UNSPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Pentium

III Processor for the SC242 at

450 MHz to 733 MHz

Datasheet

Product Features

Available in 733, 667, 600B, 600EB, and

533B MHz speeds suport a 133 MHz

system bus (‘B’ denotes support for a 133

MHz system bus; ‘E’ denotes support for

Advanced Transfer Cache and Advanced

System Buffering)

Available in 700, 650, 600E, 600, 550, 500,

and 450 MHz speeds support a 100 MHz

system bus (‘E’ denotes support for

Advanced Transfer Cache and Advanced

System Buffering)

Available in versions that incorporate

256 KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache with Error

Correcting Code (ECC)) or versions that

incorporate a discrete, half-speed, 512 KB

in-package L2 cache with ECC

Dual Independent Bus (DIB) architecture

increases bandwidth and performance over

single-bus processors

Internet Streaming SIMD Extensions for

enhanced video, sound and 3D

performance

Binary compatible with applications

running on previous members of the Intel

microprocessor line

Dynamic execution micro architecture

Power Management capabilities

— System Management mode

— Multiple low-power states

Intel Processor Serial Number

Optimized for 32-bit applications running

on advanced 32-bit operating systems

Single Edge Contact Cartridge (S.E.C.C.)

and S.E.C.C.2 packaging technology; the

S.E.C. cartridges deliver high performance

with improved handling protection and

socketability

Integrated high performance 16 KB

instruction and 16 KB data, nonblocking,

level one cache

Enables systems which are scaleable up to

two processors

Error-correcting code for System Bus data

The Pentium

III

processor is designed for high-performance desktops and for workstations and

servers. It is binary compatible with previous Intel Architecture processors. The Pentium

III

processor provides great performance for applications running on advanced operating systems

such as Windows* 98, Windows NT and UNIX*. This is achieved by integrating the best

attributes of Intel processors—the dynamic execution, Dual Independent Bus architecture plus

Intel MMX™ technology and Internet Streaming SIMD Extentions—bringing a new level of

performance for systems buyers. The Pentium

III

processor is scaleable to two processors in a

multiprocessor system and extends the power of the Pentium II processor with performance

headroom for business media, communication and internet capabilities. Systems based on

Pentium

III

processors also include the latest features to simplify system management and lower

the cost of ownership for large and small business environments. The Pentium

III

processor

offers great performance for today’s and tomorrow’s applications.

October 1999

Order Number:

244452-004

Pentium

III Processor for the SC242 at 450 MHz to 733 MHz

Contents

1.0

Introduction......................................................................................................................... 9

1.1

Terminology.........................................................................................................10

1.1.1 S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology ..................10

1.1.2 Processor Naming Convention...............................................................11

Related Documents.............................................................................................11

Processor System Bus and V

REF .......................................................................................... 13

Clock Control and Low Power States..................................................................14

2.2.1 Normal State—State 1 ...........................................................................15

2.2.2 AutoHALT Powerdown State—State 2...................................................15

2.2.3 Stop-Grant State—State 3 .....................................................................15

2.2.4 HALT/Grant Snoop State—State 4 ........................................................16

2.2.5 Sleep State—State 5..............................................................................16

2.2.6 Deep Sleep State—State 6 ....................................................................16

2.2.7 Clock Control..........................................................................................17

Power and Ground Pins ......................................................................................17

Decoupling Guidelines ........................................................................................17

2.4.1 Processor VCC

CORE

Decoupling............................................................17

2.4.2 Processor System Bus AGTL+ Decoupling............................................18

Processor System Bus Clock and Processor Clocking .......................................18

Voltage Identification ...........................................................................................18

Processor System Bus Unused Pins...................................................................20

Processor System Bus Signal Groups ................................................................20

2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................21

2.8.2 System Bus Frequency Select Signal (BSEL0)......................................21

Test Access Port (TAP) Connection....................................................................23

Maximum Ratings................................................................................................24

Processor DC Specifications...............................................................................25

AGTL+ System Bus Specifications .....................................................................29

System Bus AC Specifications ............................................................................30

BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and

Measurement Guidelines ....................................................................................39

AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and

Measurement Guidelines ....................................................................................40

3.2.1 Overshoot/Undershoot Magnitude .........................................................40

3.2.2 Overshoot/Undershoot Pulse Duration...................................................41

3.2.3 Overshoot/Undershoot Activity Factor....................................................41

3.2.4 Reading Overshoot/Undershoot Specification Tables............................42

3.2.5 Determining if a System meets the Overshoot/Undershoot

Specifications .........................................................................................43

AGTL+ and Non-AGTL+ Ringback Specifications and Measurement

Guidelines ...........................................................................................................45

3.3.1 Settling Limit Guideline...........................................................................47

1.2

2.0

2.1

2.2

Electrical Specifications....................................................................................................13

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

3.0

3.1

3.2

Signal Quality Specifications ............................................................................................39

3.3

Datasheet

Pentium

III Processor for the SC242 at 450 MHz to 733 MHz

4.0

Thermal Specifications and Design Considerations......................................................... 48

4.1

Thermal Specifications........................................................................................ 49

4.1.1 Thermal Diode........................................................................................ 51

S.E.C.C. Mechanical Specifications.................................................................... 52

S.E.C.C.2 Mechanical Specification.................................................................... 59

S.E.C.C.2 Structural Mechanical Specification ................................................... 65

Processor Package Materials Information .......................................................... 67

Intel

Pentium

III Processor Signal Listing........................................................ 67

Intel

Pentium

III Processor Core Pad to Substrate Via Assignments .............. 76

5.6.1 Processor Core Pad Via Assignments (CPUID 067xh).......................... 76

5.6.2 Processor Core Signal Assignments (CPUID 067xh) ............................ 76

5.6.3 Processor Core Pad Via Assignments (CPUID 068xh).......................... 89

Introduction ......................................................................................................... 90

Fan Heatsink Mechanical Specifications............................................................. 90

6.2.1 Boxed Processor Fan Heatsink Dimensions .......................................... 90

6.2.2 Boxed Processor Fan Heatsink Weight.................................................. 92

6.2.3 Boxed Processor Retention Mechanism ................................................ 92

Fan Heatsink Electrical Requirements ................................................................ 93

6.3.1 Fan Heatsink Power Supply ................................................................... 93

Fan Heatsink Thermal Specifications.................................................................. 94

6.4.1 Boxed Processor Cooling Requirements ............................................... 94

Alphabetical Signals Reference .......................................................................... 95

Signal Summaries ............................................................................................. 102

5.0

S.E.C.C. and S.E.C.C.2 Mechanical Specifications......................................................... 52

5.1

5.2

5.3

5.4

5.5

5.6

6.0

Boxed Processor Specifications....................................................................................... 90

6.1

6.2

6.3

6.4

7.0

Intel

Pentium

III Processor Signal Description ............................................................. 95

7.1

7.2

Datasheet

Pentium

III Processor for the SC242 at 450 MHz to 733 MHz

Figures

Second Level (L2) Cache Implementation ........................................................... 9

AGTL+ Bus Topology ..........................................................................................14

Stop Clock State Machine ...................................................................................14

BSEL[1:0] Example for a 100 MHz System Design

(100 MHz Processor Installed) ............................................................................22

BSEL[1:0] Example for a 100/133 MHz Capable System

(100 MHz Processor Installed) ............................................................................23

BSEL[1:0] Example for a 100/133 MHz Capable System

(133 MHz Processor Installed) ............................................................................23

BCLK, PICCLK, and TCK Generic Clock Waveform...........................................36

System Bus Valid Delay Timings ........................................................................36

System Bus Setup and Hold Timings..................................................................37

System Bus Reset and Configuration Timings....................................................37

Power-On Reset and Configuration Timings.......................................................37

Test Timings (TAP Connection) ..........................................................................38

Test Reset Timings .............................................................................................38

BCLK and PICCLK Generic Clock Waveform .....................................................39

Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot

Waveform ............................................................................................................45

Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................47

Signal Overshoot/Undershoot, Settling Limit, and Ringback ..............................47

S.E.C.Cartridge — 3-Dimensional View..............................................................48

S.E.C.Cartridge 2 — Substrate View ..................................................................49

Processor Functional Die Layout (CPUID 068xh) ...............................................50

S.E.C.C. Packaged Processor — Multiple Views................................................52

S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions ....53

S.E.C.C. Packaged Processor — Bottom View Dimensions...............................53

S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,

and Cover Lug Dimensions .................................................................................54

S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,

and Cover Detail Dimensions (Reference Dimensions Only)..............................55

S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment

Detail Dimensions ...............................................................................................56

S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment

Detail Dimensions, Continued .............................................................................57

S.E.C.C. Packaged Processor Substrate — Edge Finger Contact Dimensions .57

S.E.C.C. Packaged Processor Substrate — Edge Finger Contact

Dimensions, Detail A ...........................................................................................58

Intel

Pentium® III Processor Markings (S.E.C.C. Packaged Processor)...........58

S.E.C.C.2 Packaged Processor — Multiple Views..............................................59

S.E.C.C.2 Packaged Processor Assembly — Primary View...............................60

S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ......60

S.E.C.C.2 Packaged Processor Assembly — Heat Sink Attach Boss Section ...61

S.E.C.C.2 Packaged Processor Assembly — Side View ....................................61

Detail View of Cover in the Vicinity of the Substrate Attach Features.................61

S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact

Dimensions..........................................................................................................62

S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact

Dimensions (Detail A)..........................................................................................62

Datasheet

80525PY550512 Related Products

	80525PY550512	80526PY667256	80525PY533256	80525PY500512	80526PY733256	80525PY600512	80525PY533512	80526PY600512
Description	Microprocessor, CMOS	Microprocessor, 32-Bit, 667MHz, CMOS	Microprocessor, 32-Bit, 533MHz, CMOS	Microprocessor, CMOS	Microprocessor, 32-Bit, 733MHz, CMOS	Microprocessor, CMOS	Microprocessor, 32-Bit, 533MHz, CMOS	Microprocessor, 32-Bit, 600MHz, CMOS
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	36	36	36	36	36	36	36	36
boundary scan	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	550 MHz	667 MHz	533 MHz	500 MHz	733 MHz	600 MHz	533 MHz	600 MHz
External data bus width	64	64	64	64	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	R-XXMA-X	R-XXMA-X	R-XXMA-X	R-XXMA-X	R-XXMA-X	R-XXMA-X	R-XXMA-X	R-XXMA-X
low power mode	YES	YES	YES	YES	YES	YES	YES	YES
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage	2 V	1.65 V	2 V	2 V	1.65 V	2.05 V	2 V	2.05 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
Terminal location	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Maker	-	Intel	-	Intel	Intel	Intel	Intel	Intel
bit size	-	32	32	-	32	-	32	32
speed	-	667 MHz	533 MHz	-	733 MHz	-	533 MHz	600 MHz

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