S E M I C O N D U C T O R
HIP4081A
80V/2.5A Peak, High Frequency
Full Bridge FET Driver
Description
The HIP4081A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081A can drive every
possible switch combination except those which would
cause a shoot-through condition. The HIP4081A can switch
at frequencies up to 1MHz and is well suited to driving Voice
Coil Motors, high-frequency Class D audio amplifiers, and
power supplies.
For example, the HIP4081A can drive medium voltage brush
motors, and two HIP4081As can be used to drive high per-
formance stepper motors, since the short minimum “on-time”
can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.
A similar part, the HIP4080A, includes an on-chip input com-
parator to create a PWM signal from an external triangle
wave and to facilitate “hysteresis mode” switching.
The Application Note for the HIP4081A is the AN9405.
November 1996
Features
• Independently Drives 4 N-Channel FET in Half Bridge
or Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95V
DC
• Drives 1000pF Load at 1MHz in Free Air at 50
o
C with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels
• Very Low Power Consumption
• Undervoltage Protection
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Class D Audio Power Amplifiers
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Ordering Information
PART
NUMBER
HIP4081AIP
HIP4081AIB
TEMP RANGE
(
o
C)
-40 to 85
-40 to 85
PACKAGE
20 Ld PDIP
20 Ld SOIC (W)
PKG. NO.
E20.3
M20.3
Pinout
HIP4081A (PDIP, SOIC)
TOP VIEW
BHB
BHI
DIS
V
SS
BLI
ALI
AHI
HDEL
LDEL
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
BHO
BHS
BLO
BLS
V
DD
V
CC
ALS
ALO
AHS
AHO
Application Block Diagram
80V
12V
BHO
BHS
BHI
BLI
HIP4081A
ALI
AHI
ALO
AHS
AHO
BLO
LOAD
AHB 10
GND
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
File Number
3659.5
1
HIP4081A
Functional Block Diagram
UNDER-
VOLTAGE
(1/2 HIP4081A)
AHB
10
DRIVER
11
AHS
12
TURN-ON
DELAY
D
BS
TO V
DD
(PIN 16)
AHO
C
BS
HIGH VOLTAGE BUS
≤
80V
DC
CHARGE
PUMP
LEVEL SHIFT
AND LATCH
V
DD
16
AHI
7
DIS
3
15
V
CC
DRIVER
ALI
6
TURN-ON
DELAY
13
ALO
C
BF
+12V
DC
BIAS
SUPPLY
ALS
14
HDEL
LDEL
V
SS
8
9
4
Typical Application
(PWM Mode Switching)
80V
1 BHB
HIP4081/HIP4081A
12V
DIS
PWM
INPUT
2 BHI
3 DIS
4 V
SS
5 BLI
6 ALI
7 AHI
8 HDEL
9 LDEL
10 AHB
BHO 20
BHS 19
BLO 18
BLS 17
V
DD
16
V
CC
15
ALS 14
ALO 13
AHS 12
AHO 11
12V
LOAD
GND
TO OPTIONAL
CURRENT CONTROLLER
-
+
6V
GND
2
HIP4081A
Absolute Maximum Ratings
Supply Voltage, V
DD
and V
CC
. . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25
o
C to 125
o
C)
Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55
o
C to 125
o
C)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . . . . V
AHS, BHS
-0.3V to V
AHS, BHS
+V
DD
Voltage on ALO, BLO . . . . . . . . . . . . . V
ALS, BLS
-0.3V to V
CC
+0.3V
Voltage on AHO, BHO . . . . . . . V
AHS, BHS
-0.3V to V
AHB, BHB
+0.3V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
NOTE: All Voltages relative to V
SS
, unless otherwise specified.
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125
o
C
Lead Temperature (Soldering 10s)) . . . . . . . . . . . . . . . . . . . . 300
o
C
(For SOIC - Lead Tips Only
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Supply Voltage, V
DD
and V
CC
. . . . . . . . . . . . . . . . . . . +9.5V to +15V
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . . . . V
AHS, BHS
+5V to V
AHS, BHS
+15V
Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA
Operating Ambient Temperature Range . . . . . . . . . . . -40
o
C to 85
o
C
Electrical Specifications
V
DD
= V
CC
= V
AHB
= V
BHB
= 12V, V
SS
= V
ALS
= V
BLS
= V
AHS
= V
BHS
= 0V, R
HDEL
= R
LDEL
= 100K and
T
A
= 25
o
C, Unless Otherwise Specified
25
o
C
MAX
T
JS
= -40
o
C
TO 125
o
C
MIN
MAX
UNITS
T
J
=
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
SUPPLY CURRENTS AND CHARGE PUMPS
V
DD
Quiescent Current
V
DD
Operating Current
V
CC
Quiescent Current
V
CC
Operating Current
AHB, BHB Quiescent Current -
Qpump Output Current
AHB, BHB Operating Current
AHS, BHS, AHB, BHB Leakage
Current
AHB-AHS, BHB-BHS Qpump
Output Voltage
I
DD
I
DDO
I
CC
I
CCO
I
AHB
, I
BHB
All inputs = 0V
Outputs switching f = 500kHz
All Inputs = 0V, I
ALO
= I
BLO
= 0
f = 500kHz, No Load
All Inputs = 0V, I
AHO
= I
BHO
= 0
V
DD
= V
CC
= V
AHB
= V
BHB
= 10V
8.5
9.5
-
1
-50
0.6
-
11.5
10.5
12.5
0.1
1.25
-30
1.2
0.02
12.6
14.5
15.5
10
2.0
-11
1.5
1.0
14.0
7.5
8.5
-
0.8
-60
0.5
-
10.5
14.5
15.5
20
3
-10
1.9
10
14.5
mA
mA
µA
mA
µA
mA
µA
V
I
AHBO
, I
BHBO
f = 500kHz, No Load
I
HLK
V
AHB
-V
AHS
V
BHB
-V
BHS
V
BHS
= V
AHS
= 80V,
V
AHB
= V
BHB
= 93V
I
AHB
= I
AHB
= 0, No Load
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current
High Level Input Current
I
IL
I
IH
V
IN
= 0V, Full Operating Conditions
V
IN
= 5V, Full Operating Conditions
V
IL
V
IH
Full Operating Conditions
Full Operating Conditions
-
2.5
-
-130
-1
-
-
35
-100
-
1.0
-
-
-75
+1
-
2.7
-
-135
-10
0.8
-
-
-65
+10
V
V
mV
µA
µA
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage
V
HDEL
, V
LDEL
I
HDEL
= I
LDEL
= -100µA
4.9
5.1
5.3
4.8
5.4
V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current
V
OL
V
CC
-V
OH
I
O
+
I
O
-
I
OUT
= 100mA
I
OUT
= -100mA
V
OUT
= 0V
V
OUT
= 12V
0.7
0.8
1.7
1.7
0.85
0.95
2.6
2.4
1.0
1.1
3.8
3.3
0.5
0.5
1.4
1.3
1.1
1.2
4.1
3.6
V
V
A
A
3
HIP4081A
Electrical Specifications
V
DD
= V
CC
= V
AHB
= V
BHB
= 12V, V
SS
= V
ALS
= V
BLS
= V
AHS
= V
BHS
= 0V, R
HDEL
= R
LDEL
= 100K and
T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
25
o
C
MAX
9.4
8.9
0.65
T
JS
= -40
o
C
TO 125
o
C
MIN
8.0
7.5
0.2
MAX
9.5
9.0
0.7
UNITS
V
V
V
T
J
=
PARAMETER
Undervoltage, Rising Threshold
Undervoltage, Falling Threshold
Undervoltage, Hysteresis
SYMBOL
UV+
UV-
HYS
TEST CONDITIONS
MIN
8.1
7.6
0.25
TYP
8.8
8.3
0.4
Switching Specifications
V
DD
= V
CC
= V
AHB
= V
BHB
= 12V, V
SS
= V
ALS
= V
BLS
= V
AHS
= V
BHS
= 0V, R
HDEL
= R
LDEL
= 10K,
C
L
= 1000pF.
25
o
C
MAX
60
70
70
90
25
25
-
-
-
-
75
85
70
550
620
T
JS
= -40
o
C
TO 125
o
C
MIN
-
-
-
-
-
-
50
40
40
30
-
-
-
200
-
MAX UNITS
80
90
90
110
35
35
-
-
-
-
95
105
90
600
690
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
J
=
PARAMETER
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
Rise Time
Fall Time
Turn-on Input Pulse Width
Turn-off Input Pulse Width
Turn-on Output Pulse Width
Turn-off Output Pulse Width
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
Refresh Pulse Width (ALO and BLO)
Disable to Upper Enable (DIS - AHO and BHO)
SYMBOL
T
LPHL
T
HPHL
T
LPLH
T
HPLH
T
R
T
F
T
PWIN-ON
T
PWIN-OFF
T
PWOUT-ON
T
PWOUT-OFF
T
DISLOW
T
DISHIGH
T
DLPLH
T
REF-PW
T
UEN
TRUTH TABLE
INPUT
ALI, BLI
X
1
0
0
X
NOTE:
AHI, BHI
X
X
1
0
X
U/V
X
0
0
0
1
DIS
1
0
0
0
X
R
HDEL
= R
LDEL
= 10K
R
HDEL
= R
LDEL
= 10K
R
HDEL
= R
LDEL
= 10K
R
HDEL
= R
LDEL
= 10K
R
HDEL
= R
LDEL
= 10K
R
HDEL
= R
LDEL
= 10K
TEST CONDITIONS
MIN
-
-
-
-
-
-
50
40
40
30
-
-
-
240
-
TYP
30
35
45
60
10
10
-
-
-
-
45
55
40
410
450
OUTPUT
ALO, BLO
0
1
0
0
0
AHO, BHO
0
0
1
0
0
X signifies that input can be either a “1” or “0”.
4
HIP4081A
Pin Descriptions
PIN
NUMBER
1
SYMBOL
BHB
DESCRIPTION
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V
DD
). An internal 100µA
pull-up to V
DD
will hold BHI high, so no connection is required if high-side and low-side outputs are to be con-
trolled by the low-side input.
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of
0V to 15V (no greater than V
DD
). An internal 100µA pull-up to V
DD
will hold DIS high if this pin is not driven.
Chip negative supply, generally will be ground.
B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels
of 0V to 15V (no greater than V
DD
). An internal 100µA pull-up to V
DD
will hold BLI high if this pin is not driven.
A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels
of 0V to 15V (no greater than V
DD
). An internal 100µA pull-up to V
DD
will hold ALI high if this pin is not driven.
A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI
high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V
DD
). An internal 100µA
pull-up to V
DD
will hold AHI high, so no connection is required if high-side and low-side outputs are to be con-
trolled by the low-side input.
High-side turn-on DELay. Connect resistor from this pin to V
SS
to set timing current that defines the turn-on de-
lay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guar-
antees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is
approximately 5.1V.
Low-side turn-on DELay. Connect resistor from this pin to V
SS
to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
A High-side Output. Connect to gate of A High-side power MOSFET.
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
A Low-side Output. Connect to gate of A Low-side power MOSFET.
A Low-side Source connection. Connect to source of A Low-side power MOSFET.
Positive supply to gate drivers. Must be same potential as V
DD
(Pin 16). Connect to anodes of two bootstrap
diodes.
Positive supply to lower gate drivers. Must be same potential as V
CC
(Pin 15). De-couple this pin to V
SS
(Pin 4).
B Low-side Source connection. Connect to source of B Low-side power MOSFET.
B Low-side Output. Connect to gate of B Low-side power MOSFET.
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
B High-side Output. Connect to gate of B High-side power MOSFET.
2
BHI
3
DIS
4
5
V
SS
BLI
6
ALI
7
AHI
8
HDEL
9
LDEL
10
AHB
11
12
13
14
15
16
17
18
19
20
AHO
AHS
ALO
ALS
V
CC
V
DD
BLS
BLO
BHS
BHO
5
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