Intel StrataFlash Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
®
Datasheet
Product Features
■
High performance Read-While-Write/Erase
■
Software
— 85 ns initial access
— 54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(Buffered EFP): 5 µs/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming at 7 µs/byte (Typ)
■
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Multiple 16-Mbit partitions: 256Mb devices
— Four 16-Kword parameter blocks: top or
bottom configurations
— 64-Kword main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status register for partition and device status
■
Power
— 1.7 V - 2.0 V V
CC
operation
— I/O voltage: 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby current: 25 µA (Typ)
— 4-Word synchronous read current: 17 mA (Typ)
at 54 MHz
— Automatic Power Savings (APS) mode
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
■
Security
•
OTP space:
— 64 unique device identifier bits
— 64 user-programmable OTP bits
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: V
PP
= GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
■
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
■
Density and Packaging
— 64-, 128- and 256-Mbit density in VF BGA
packages
— 128/0, and 256/0 Density in SCSP
— 16-bit wide data bus
The Intel StrataFlash
®
wireless memory (L18) device is the latest generation of Intel
StrataFlash
®
memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows two processors to interleave code operations while program and erase
operations take place in the background. The 8-Mbit partitions allow system designers to choose
the size of the code and data segments. The L18 wireless memory device is manufactured using
Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale
packaging.
Notice:
This document contains information on products in the design phase of development.
The information here is subject to change without notice. Verify with your local Intel sales office
that you have the latest datasheet before finalizing a design.
251902-007
September 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The Intel StrataFlash® Wireless Memory (L18) datasheet may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2004, Intel Corporation
* Other names and brands may be claimed as the property of others.
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28F640L18, 28F128L18, 28F256L18
Contents
1.0
Introduction
..................................................................................................................7
1.1
1.2
1.3
Nomenclature ........................................................................................................7
Acronyms ..............................................................................................................7
Conventions ..........................................................................................................8
2.0
3.0
Functional Overview
.................................................................................................9
Package Information
...............................................................................................10
3.1
3.2
3.3
VF BGA Packages ..............................................................................................10
SCSP Package....................................................................................................12
Intel UT-SCSP Package ...................................................................................13
Signal Ballout ......................................................................................................14
4.1.1 VF BGA Package Ballout .......................................................................14
4.1.2 SCSP Package Ballout...........................................................................16
Signal Descriptions..............................................................................................17
4.2.1 VF BGA Package Signal Descriptions ...................................................17
4.2.2 128/0 and 256/0 SCSP Package Signal Descriptions............................19
Memory Map .......................................................................................................20
4.0
Ballout and Signal Descriptions
........................................................................14
4.1
4.2
4.3
5.0
Maximum Ratings and Operating Conditions
..............................................23
5.1
5.2
Absolute Maximum Ratings.................................................................................23
Operating Conditions...........................................................................................23
DC Current Characteristics .................................................................................24
DC Voltage Characteristics .................................................................................25
AC Test Conditions .............................................................................................26
Capacitance ........................................................................................................27
AC Read Specifications (VCCQ = 1.35 V – 2.0 V) ..............................................28
AC Read Specifications for 64-Mb and 128-Mb Densities
(VCCQ = 1.7 V – 2.0 V).......................................................................................29
AC Read Specifications for 256-Mb Density .......................................................30
AC Write Specifications.......................................................................................35
Program and Erase Characteristics ....................................................................39
Power Up and Down ...........................................................................................40
Reset ...................................................................................................................40
Power Supply Decoupling ...................................................................................41
Automatic Power Saving (APS)...........................................................................41
6.0
Electrical Specifications
........................................................................................24
6.1
6.2
7.0
AC Characteristics
...................................................................................................26
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.0
Power and Reset Specifications
........................................................................40
8.1
8.2
8.3
8.4
9.0
Device Operations
...................................................................................................42
9.1
Bus Operations....................................................................................................42
9.1.1 Reads .....................................................................................................43
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28F640L18, 28F128L18, 28F256L18
9.2
9.3
9.1.2 Writes ..................................................................................................... 43
9.1.3 Output Disable ....................................................................................... 43
9.1.4 Standby .................................................................................................. 43
9.1.5 Reset ...................................................................................................... 43
Device Commands .............................................................................................. 44
Command Definitions .......................................................................................... 45
Asynchronous Page-Mode Read ........................................................................ 48
Synchronous Burst-Mode Read .......................................................................... 48
10.2.1 Burst Suspend........................................................................................ 49
Read Configuration Register (RCR).................................................................... 49
10.3.1 Read Mode............................................................................................. 50
10.3.2 Latency Count ........................................................................................ 51
10.3.3 WAIT Polarity ......................................................................................... 53
10.3.3.1WAIT Signal Function ............................................................... 53
10.3.4 Data Hold ............................................................................................... 54
10.3.5 WAIT Delay ............................................................................................ 55
10.3.6 Burst Sequence...................................................................................... 55
10.3.7 Clock Edge ............................................................................................. 56
10.3.8 Burst Wrap ............................................................................................. 56
10.3.9 Burst Length ........................................................................................... 56
Word Programming ............................................................................................. 57
11.1.1 Factory Word Programming ................................................................... 58
Buffered Programming ........................................................................................ 58
Buffered Enhanced Factory Programming .......................................................... 59
11.3.1 Buffered EFP Requirements and Considerations .................................. 59
11.3.2 Buffered EFP Setup Phase .................................................................... 60
11.3.3 Buffered EFP Program/Verify Phase...................................................... 60
11.3.4 Buffered EFP Exit Phase ....................................................................... 61
Program Suspend ............................................................................................... 61
Program Resume ................................................................................................ 62
Program Protection ............................................................................................. 62
Block Erase ......................................................................................................... 63
Erase Suspend.................................................................................................... 63
Erase Resume .................................................................................................... 64
Erase Protection.................................................................................................. 64
Block Locking ...................................................................................................... 65
13.1.1 Lock Block .............................................................................................. 65
13.1.2 Unlock Block .......................................................................................... 65
13.1.3 Lock-Down Block ................................................................................... 65
13.1.4 Block Lock Status................................................................................... 66
13.1.5 Block Locking During Suspend .............................................................. 66
Protection Registers ............................................................................................ 67
13.2.1 Reading the Protection Registers .......................................................... 68
10.0
Read Operations
....................................................................................................... 48
10.1
10.2
10.3
11.0
Programming Operations
..................................................................................... 57
11.1
11.2
11.3
11.4
11.5
11.6
12.0
Erase Operations
..................................................................................................... 63
12.1
12.2
12.3
12.4
13.0
Security Modes
......................................................................................................... 65
13.1
13.2
4
28F640L18, 28F128L18, 28F256L18
13.2.2 Programming the Protection Registers ..................................................69
13.2.3 Locking the Protection Registers............................................................69
14.0
Dual-Operation Considerations
..........................................................................70
14.1
14.2
Memory Partitioning ............................................................................................70
Read-While-Write Command Sequences ...........................................................70
14.2.1 Simultaneous Operation Details.............................................................71
14.2.2 Synchronous and Asynchronous Read-While-Write Characteristics
and Waveforms ......................................................................................71
14.2.2.1Write operation to asynchronous read transition .......................71
14.2.2.2Write to synchronous read operation transition.........................72
14.2.2.3Write Operation with Clock Active .............................................72
14.2.3 Read Operation During Buffered Programming .....................................72
Simultaneous Operation Restrictions ..................................................................73
Read Status Register ..........................................................................................74
15.1.1 Clear Status Register .............................................................................75
Read Device Identifier .........................................................................................75
CFI Query............................................................................................................76
14.3
15.0
Special Read States
................................................................................................74
15.1
15.2
15.3
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix F
Write State Machine (WSM)
...........................................................................77
Flowcharts
............................................................................................................84
Common Flash Interface
................................................................................92
Additional Information
................................................................................... 103
Ordering Information for VF BGA Package
.......................................... 104
Ordering Information for SCSP Package
............................................... 105
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