Features
•
4.5V to 5.5V Read/Write
•
Access Time - 70 ns
•
Sector Erase Architecture
– Thirty 32K Word (64K byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K byte) Sectors with Individual Write Lockout
– Two 16K Word (32K byte) Sectors with Individual Write Lockout
Fast Word Program Time - 10
µ
s
Fast Sector Erase Time - 200 ms
Dual Plane Organization, Permitting Concurrent Read while Program/Erase
– Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
– Memory Plane B: Twenty-Four 32K Word Sectors
Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low Power Operation
– 40 mA Active
– 10
µ
A Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
RESET Input for Device Initialization
Sector Program Unlock Command
TSOP, CBGA, and
µ
BGA Package Options
Top or Bottom Boot Block Configuration Available
•
•
•
•
•
•
•
•
•
•
16-Megabit
(1M x 16/2M x 8)
5-volt Only
Flash Memory
AT49F1604
AT49F1604T
AT49F1614
AT49F1614T
Advance
Information
AT49BV16X4(T)
AT49BV1604
Description
The AT49F16X4(T) is a 5.0 volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 blocks for
erase operations. The device is offered in 48-pin TSOP and 48-ball
µBGA
packages.
The device has CE, and OE control signals to avoid any bus contention. This device
can be read or reprogrammed using a single 5.0V power supply, making it ideally
suited for in-system programming.
(continued)
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Don’t Connect
Rev. 0977B–06/98
1
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCC
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
µBGA
Top View (Ball Down)
1
A
A13
A11
A10
A12
I/O14
I/O15
I/O7
A8
WE
A9
I/O5
I/O6
I/O13
NC
RST
NC
I/O11
I/O12
I/O4
NC
A18
NC
I/O2
I/O3
VCC
A19
A17
A6
I/O8
I/O9
I/O10
A7
A5
A3
CE
I/O0
I/O1
A4
A2
A1
A0
GND
OE
2
3
4
5
6
7
8
B
A14
AT49F1604(T)
C
A15
D
A16
E
VCC
F
GND
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
CBGA Top View
H
G
F
E
D
C
B
A
1
VSS
I/O1
OE
I/O9
I/O11
VCC
I/O13
I/O15
/A-1
CE
I/O8
I/O10
I/O12
I/O14
BYTE
A0
I/O0
I/O2
I/O5
I/O7
A16
A1
A5
NC
A19
A11
A15
A2
A6
A18
NC
A10
A14
A4
A17
A3
2
A7
AT49F1614(T)
I/O3
I/O4
I/O6
VSS
NC RDY/BUSY
RESET
A8
A12
WE
3
4
5
A9
6
A13
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and V
CC
.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is detected by the Ready/Busy pin, Data polling, or by
the toggle bit.
A six byte command (bypass unlock) sequence to remove
the requirement of entering the three byte program
sequence is offered to further improve programming time.
After entering the six byte code, only single pulses on the
write control lines are required for writing into the device.
This mode (single pulse byte/word program) is exited by
2
AT49F16X4(T)
AT49F16X4(T)
powering down the device, or by pulsing the RESET pin
low and then bringing it back to V
CC
. Erase and Erase Sus-
pend/Resume commands will not work while in this mode;
if entered they will result in data being programmed into the
device. It is not recommended that the six byte code reside
in the software of the final product but only exist in external
programming code.
The BYTE pin controls whether the device data I/O pins
operate in the byte or word configuration. If the BYTE pin is
set at logic “1”, the device is in word configuration, I/O0-
I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0-I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8-I/O14 are
tri-stated, and the I/O15 pin is used as an input for the LSB
(A-1) address function.
Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
A0 - A19
INPUT
BUFFER
DATA
REGISTER
IDENTIFIER
REGISTER
STATUS
REGISTER
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
CE
WE
OE
RESET
BYTE
RDY/BUSY
WRITE STATE
MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE
VOLTAGE SWITCH
VCC
GND
X-DECODER
PLANE B
SECTORS
PLANE A SECTORS
Device Operation
READ:
The AT49F16X4(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
COMMAND SEQUENCES:
When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
RESET:
A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
3
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V
±
0.5V input
signal to the RESET pin any sector can be reprogrammed
even if the sector lockout feature has been enabled (see
Sector Programming Lockout Override section).
ERASURE:
Before a byte/word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi-
cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.
CHIP ERASE:
The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is t
EC
.
If the sector lockout has been enabled, the Chip Erase will
not erase the data in the sector that has been locked; it will
erase only the unprotected sectors. After the chip erase,
the device will return to the read or standby mode.
SECTOR ERASE:
As an alternative to a full chip erase, the
device is organized into forty sectors (SA0 - SA39) that can
be individually erased. The Sector Erase command is a six
bus cycle operation. The sector address is latched on the
falling WE edge of the sixth cycle while the 30H data input
command is latched on the rising edge of WE. The sector
erase starts after the rising edge of WE of the sixth cycle.
The erase operation is internally controlled; it will automati-
cally time to completion. The maximum time to erase a sec-
tion is t
SEC
. When the sector programming lockout feature
is not enabled, the sector will erase (from the same sector
erase command). Once a sector has been protected, data
in the protected sectors cannot be changed unless the
RESET pin is taken to 12V
±
0.5V. An attempt to erase a
sector that has been protected will result in the operation
terminating in 2
µs.
BYTE/WORD PROGRAMMING:
Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or on a word-by-word basis. Programming is accomplished
via the internal device command register and is a 4-bus
cycle operation. The device will automatically generate the
required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified t
BP
cycle time. The DATA polling feature or the
toggle bit feature may be used to indicate the end of a pro-
gram cycle.
SECTOR PROGRAMMING LOCKOUT:
Each sector has a
programming lockout feature. This feature prevents pro-
gramming of data in the designated sectors once the fea-
ture has been enabled. These sectors can contain secure
code that is used to bring up the system. Enabling the lock-
out feature will allow the boot code to stay in the device
while data in the rest of the device is updated. This feature
does not have to be activated; any sector’s usage as a
write protected region is optional to the user.
Once the feature is enabled, the data in the protected sec-
tors can no longer be erased or programmed when input
levels of 5.5V or less are used. Data in the remaining sec-
tors can still be changed through the regular programming
method. To activate the lockout feature, a series of six pro-
gram commands to specific addresses with specific data
must be performed. Please refer to the Command Defini-
tions table.
SECTOR PROGRAMMING LOCKOUT OVERRIDE:
The
user can override the sector programming lockout by taking
the RESET pin to 12V
±
0.5V. By doing this protected data
can be altered through a chip erase, sector erase or
byte/word programming. When the RESET pin is brought
back to TTL levels the sector programming lockout feature
is again active.
ERASE SUSPEND/ERASE RESUME:
The erase suspend
command allows the system to interrupt a sector erase
operation and then program or read data from a different
sector within the same plane. Since this device has a dual
plane architecture, there is no need to use the erase sus-
pend feature while erasing a sector when you want to read
data from a sector in the other plane. After the erase sus-
pend command is given, the device requires a maximum
time of 15
µs
to suspend the erase operation. After the
erase operation has been suspended, the plane which con-
tains the suspended sector enters the erase-suspend-read
mode. The system can then read data or program data to
any other sector within the device. An address is not
required during the erase suspend command. During a
sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write
the erase resume command. The erase resume command
is a one bus cycle command, which does require the plane
address (determined by A18 and A19). The device also
supports an erase suspend during a complete chip erase.
While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The com-
mand sequence for a chip erase suspend and a sector
erase suspend are the same.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
4
AT49F16X4(T)
AT49F16X4(T)
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49F16X4(T) features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte/word loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle. Please see “Status Bit Table” for more details.
T O G G L E B I T :
I n a d d i t i o n t o DATA p o l l i n g t h e
AT49F16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2 which can be
used in conjunction with the toggle bit which is available on
I/O6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the
I/O2 bit toggling. Please see “Status Bit Table” for more
details.
RDY/BUSY:
An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT49F16X4(T)
in the following ways: (a) V
CC
sense: if V
CC
is below 3.8V
(typical), the program function is inhibited. (b) V
CC
power on
delay: once V
CC
has reached the V
CC
sense level, the
device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
INPUT LEVELS:
While operating with a 4.5V to 5.5V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
CC
+ 0.6V.
5
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