ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
July 2002
Advance Data Sheet
TM
Features
■
Flexible Multi-Function Block (MFB)
Architecture
•
•
•
•
•
SuperWIDE™ logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
■
Expanded In-System Programmability (ispXP™)
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or
sysCONFIG™ microprocessor interface
• Design security
■
sysCLOCK™ PLL Timing Control
■
High Speed Operation
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI-X, PCI 3.3
• GTL+
• LVDS
• LVPECL
• 3.5ns pin-to-pin delays, 285MHz f
MAX
• Deterministic timing
• Static power 20 to 50mA (1.8V) 30 to 60mA
(2.5/3.3V)
• 1.8V core for low dynamic power
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and
fine
pitch BGA packaging
■
Low Power Consumption
■
sysIO™ Interfaces
■
Easy System Integration
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX
Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
t
PD
(Propagation Delay)
t
S
(Register Set-up Time)
t
CO
(Register Clock to Out Time)
f
MAX
(Maximum Operating Frequency)
I/Os
System Gates
Packages
256 fpBGA
256
8
128K
48K
2
3.5ns
2.5ns
2.5ns
285MHz
141
75K
ispXPLD 5512MX
512
16
256K
96K
2
4.0ns
2.9ns
3.0ns
250MHz
149/193/253
150K
208 PQFP
256 fpBGA
484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX
768
24
384K
144K
2
4.5ns
3.0ns
3.0ns
225MHz
193/317
225K
256 fpBGA
484 fpBGA
1,024
32
512K
192K
2
4.5ns
3.0ns
3.0ns
225MHz
317/381
300K
484 fpBGA
672 fpBGA
www.latticesemi.com
1
5kmx_01
Lattice Semiconductor
Figure 1. ispXPLD 5000MX Block Diagram
PROGRAM
ispXPLD 5000MX Family Data Sheet
TDO
V
CCJ
GND
TMS
TCK
V
CC
ISP Port
V
CCO0
V
REF0
sysIO
Bank 0
OSA
TDI
V
CCO3
V
REF3
MFB
MFB
sysIO
Bank 3
OSA
MFB
GCLCK0
V
CCP
GNDP
GCLK1
sysIO
Bank 1
Optional
sysCONFIG
Interface
MFB
GCLCK3
Global
Routing
Pool
(GRP)
sysCLOCK
PLL 0
sysCLOCK
PLL 1
GCLK2
MFB
MFB
sysIO
Bank 2
RESET
GOE0
GOE1
V
REF2
V
CCO2
OSA
OSA
V
REF1
V
CCO1
MFB
MFB
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture
by providing
flexible
memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. In addition, sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of design-
ers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 3.5ns, 2.5ns clock-to-out delay, 2.0ns set-up time, and oper-
ating frequency up to 285MHz. This performance is coupled with low static and dynamic power consumption. The
ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the
flexibility
of the sysIO interface helps
users meet the challenge of today’s mixed voltage designs. Boundary scan testability further eases integration into
today’s complex systems. A variety of density and package options increase the likelihood of a good
fit
for a partic-
ular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool.
Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD
5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing
2
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance
access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs
are provided to allow the synthesis of new clocks and control of clock skews.
Multi-Function Block (MFB)
Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides
a
flexible
approach to implementing logic and memory that allows the designer to achieve the mix of functions that
are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are:
•
•
•
•
•
•
SuperWIDE Logic Mode
True Dual-port SRAM Mode
Pseudo Dual-port SRAM Mode
Single-port SRAM Mode
FIFO Mode
Ternary CAM Mode
The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multi-
function array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs
data along with certain control functions to the macrocells. Output signals can be routed internally for use else-
where in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various
configurations are described in more detail in the following sections.
Figure 2. MFB Block Diagram
Cascade In
CLK0
CLK1
CLK2
CLK3
Reset
To Routing
Multifunction Array
True Dual Port
RAM
(8,192 bit)
Single Port
RAM
(16,384 bit)
FIFO
(16,384 bit)
Ternary CAM
(128*48)
Logic
(68 Input * 164 Product
Term Array, 32 MC)
PTOE
Sharing
Cascade Out
3
To I/O via OSA
(16,384 bit)
32 Feedback Signals
Pseudo Dual
Port RAM
Lattice Semiconductor
Cascading For Wide Operation
ispXPLD 5000MX Family Data Sheet
In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different
cascading options. There are chains of MFBs in each device which determine those MFBs that are adjacent for the
purposes of cascading. Table 3 indicates these chains. The ispXPLD 5000MX design tools automatically cascade
blocks if required by a particular design.
Table 2. Cascading Modes For Wide Support
Mode
Logic
FIFO
CAM
Cascading Function
Input Width.
Allows two MFBs to act as a 136-input block.
Arithmetic.
Allow the carry chain to pass between two MFBs.
Memory Width Expansion.
Allows MFBs to be cascaded for greater width support.
Memory Width Expansion.
Allows up to four MFBs to be cascaded for greater width support.
Table 3. MFB Cascade Chain
Device
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
A
→
B
→
C
→
D
E
→
F
→
G
→
H
A
→
B
→
C
→
D
→
E
→
F
→
G
→
H
P
→Ο→
N
→
M
→
L
→
K
→
J
→
I
D
→
C
→
B
→
A
→
X
→
W
→
V
→
U
→
T
→
S
→
R
→
Q
E
→
F
→
G
→
H
→
I
→
J
→
K
→
L
→
M
→
N
→
O
→
P
H
→
G
→
F
→
E
→
D
→
C
→
B
→
A
→
AF
→
AE
→
AD
→
AC
→
AB
→
AA
→
Z
→
Y
I
→
J
→
K
→
L
→
M
→
N
→
O
→
P
→
Q
→
R
→
S
→
T
→
U
→
V
→
W
→
X
MFBs in Cascade Chain
SuperWIDE Logic Mode
In logic mode, each MFB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic
product terms and four control product terms. The MFB has 68 inputs from the Global Routing Pool, which are
available in both true and complement form for every product term. It is also possible to cascade adjacent MFBs to
create a block with 136 inputs. The four control product terms are used for shared reset, clock, clock enable, and
output enable functions. Figure 3 shows the overall structure of the MFB in logic mode while Figure 4 provides a
more detailed view from the perspective of a macrocell slice.
4
Lattice Semiconductor
Figure 3. MFB in SuperWIDE Logic Mode
CLK0
CLK1
CLK2
CLK3
Reset
Carry In
ispXPLD 5000MX Family Data Sheet
To Routing
Dual-OR Gate
PT Sharing Array
68 inputs 164 P-Term
32 Macrocells
68 Inputs
from
Adjacent
MFB
Shared PT Clk
Shared PT Clk En
Shared PT Reset
PTOE
Sharing
Carry Out
Figure 4. Macrocell Slice in Logic Mode AND-Array
From
GRP
From Carry-in
n-7
PT OE to
I/O Block
From
I/O Cell
PTSA Bypass
Output
to I/O Block
D
PTSA
PT Clock
Shared
PT CE
68
Q
Clk En
GRP
R/L
Shared PTCLK
CLK0
CLK1
CLK2
CLK3
Clk
P R
PT Preset
PT Reset
Shared PT Reset
Global Reset
AND Array
Dual-OR Array
To Carry-out
n+7
Macrocell
5
To I/O via OSA
68 Inputs
from
Routing
32 Macrocell Feedback Signals
AND Array
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