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LC5512MV-10F484I

Description
EE PLD, 14.3ns, 512-Cell, CMOS, PBGA484,
CategoryProgrammable logic devices    Programmable logic   
File Size826KB,43 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric Compare View All

LC5512MV-10F484I Overview

EE PLD, 14.3ns, 512-Cell, CMOS, PBGA484,

LC5512MV-10F484I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLattice
package instructionBGA, BGA484,22X22,40
Reach Compliance Codecompli
Other featuresYES
In-system programmableYES
JESD-30 codeS-PBGA-B484
JESD-609 codee0
JTAG BSTYES
Humidity sensitivity level3
Number of macro cells512
Number of terminals484
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA484,22X22,40
Package shapeSQUARE
Package formGRID ARRAY
power supply1.5/3.3,3.3 V
Programmable logic typeEE PLD
propagation delay14.3 ns
Certification statusNot Qualified
surface mountYES
technologyCMOS
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
July 2002
Advance Data Sheet
TM
Features
Flexible Multi-Function Block (MFB)
Architecture
SuperWIDE™ logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
Expanded In-System Programmability (ispXP™)
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or
sysCONFIG™ microprocessor interface
• Design security
sysCLOCK™ PLL Timing Control
High Speed Operation
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI-X, PCI 3.3
• GTL+
• LVDS
• LVPECL
• 3.5ns pin-to-pin delays, 285MHz f
MAX
• Deterministic timing
• Static power 20 to 50mA (1.8V) 30 to 60mA
(2.5/3.3V)
• 1.8V core for low dynamic power
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and
fine
pitch BGA packaging
Low Power Consumption
sysIO™ Interfaces
Easy System Integration
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX
Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
t
PD
(Propagation Delay)
t
S
(Register Set-up Time)
t
CO
(Register Clock to Out Time)
f
MAX
(Maximum Operating Frequency)
I/Os
System Gates
Packages
256 fpBGA
256
8
128K
48K
2
3.5ns
2.5ns
2.5ns
285MHz
141
75K
ispXPLD 5512MX
512
16
256K
96K
2
4.0ns
2.9ns
3.0ns
250MHz
149/193/253
150K
208 PQFP
256 fpBGA
484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX
768
24
384K
144K
2
4.5ns
3.0ns
3.0ns
225MHz
193/317
225K
256 fpBGA
484 fpBGA
1,024
32
512K
192K
2
4.5ns
3.0ns
3.0ns
225MHz
317/381
300K
484 fpBGA
672 fpBGA
www.latticesemi.com
1
5kmx_01

LC5512MV-10F484I Related Products

LC5512MV-10F484I LC5512MV-10F256I LC5512MV-10Q208I
Description EE PLD, 14.3ns, 512-Cell, CMOS, PBGA484, EE PLD, 14.3ns, 512-Cell, CMOS, PBGA256 EE PLD, 14.3ns, 512-Cell, CMOS, PQFP208
Is it Rohs certified? incompatible incompatible incompatible
Maker Lattice Lattice Lattice
package instruction BGA, BGA484,22X22,40 BGA, BGA256,16X16,40 QFP, QFP208,1.2SQ,20
Reach Compliance Code compli compli compli
Other features YES YES YES
In-system programmable YES YES YES
JESD-30 code S-PBGA-B484 S-PBGA-B256 S-PQFP-G208
JESD-609 code e0 e0 e0
JTAG BST YES YES YES
Humidity sensitivity level 3 3 3
Number of macro cells 512 512 512
Number of terminals 484 256 208
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code BGA BGA QFP
Encapsulate equivalent code BGA484,22X22,40 BGA256,16X16,40 QFP208,1.2SQ,20
Package shape SQUARE SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY FLATPACK
power supply 1.5/3.3,3.3 V 1.5/3.3,3.3 V 1.5/3.3,3.3 V
Programmable logic type EE PLD EE PLD EE PLD
propagation delay 14.3 ns 14.3 ns 14.3 ns
Certification status Not Qualified Not Qualified Not Qualified
surface mount YES YES YES
technology CMOS CMOS CMOS
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn63Pb37) Tin/Lead (Sn85Pb15)
Terminal form BALL BALL GULL WING
Terminal pitch 1 mm 1 mm 0.5 mm
Terminal location BOTTOM BOTTOM QUAD
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