L7C174
DEVICES INCORPORATED
8K x 8 Cache-Tag Static RAM
L7C174
DEVICES INCORPORATED
8K x 8 Cache-Tag Static RAM
DESCRIPTION
The
L7C174
is a high-performance,
low power CMOS static RAM opti-
mized for use as the address tag
comparator in high speed cache
memory systems. One L7C174 can be
used to map 8K cache lines into a
1 megabyte address space by compar-
ing 20 address bits organized as
13-line address bits and 7-page
address bits.
This device is available in five speed
grades with maximum address-to-
MATCH times of 12 ns to 35 ns.
Operation is from a single +5 V power
supply with power consumption only
being 300 mW (typical) at 35 ns.
Dissipation drops to 500 µW (typical)
when the memory is deselected
(Enable is high).
The L7C174 consumes only 30 µW
(typical) at 3 V allowing effective
battery backup operation. For mini-
mal power consumption, data may be
retained in inactive storage with a
supply voltage as low as 2 V.
The L7C174 provides fully asynchro-
nous (unclocked) operation with
matching access and cycle times. An
active low Chip Enable and Output
Enable along with a three state I/O
bus simplify the connection of several
chips for increased storage capacity.
Wide tag addresses are easily accom-
modated by paralleling devices and
Wire-ORing the MATCH outputs. A
low on the MATCH output indicates a
data mismatch.
Memory locations are specified on
address pins A
0
through A
12
with
functions defined in the Truth Table.
During CLEAR, the state of the I/O
pins remain completely defined by the
WE, CE, and OE control inputs. Data
In has the same polarity as Data Out.
8
5
COLUMN
ADDRESS
FEATURES
u
8K x 8 CMOS Static RAM with 8-bit
Tag Comparison Logic
u
High Speed Address-to-MATCH
— 12 ns maximum
u
High Speed Flash Clear
u
High Speed Read Access Time
— 12 ns maximum
u
Low Power Operation
Active: 300 mW typical at 35 ns
Standby: 500 µW typical
u
Data Retention at 2 V for Battery
Backup Operation
u
Available 100% Screened to
MIL-STD-883, Class B
u
Plug Compatible with IDT7174,
IDT71B74, MK48H74
u
Package Styles Available:
• 28-pin Plastic DIP
• 28-pin Ceramic DIP
• 28-pin Plastic SOJ
• 32-pin Ceramic LCC
L7C174 B
LOCK
D
IAGRAM
ROW
ADDRESS
CLEAR
BS
8
ROW
SELECT
8
8
COMPARATOR
O
8
1 (if MATCH)
The storage circuitry is organized as
8192 words by 8 bits per word and
includes an 8-bit data comparator
with MATCH output. The 8-bit data
is input/output on shared I/O pins
and comparison is performed between
8-bit incoming data and accessed
memory locations. Also provided is a
high speed CLEAR control which
clears all memory locations to zero
when activated. This allows all
address tag bits to be cleared when
powering on or when flushing the
cache.
O
I/O
7-0
WE
OE
CE
8
LE
256 x 32 x 8
MEMORY
ARRAY
COLUMN SELECT
& COLUMN SENSE
MATCH
(OPEN DRAIN)
1
Special Architecture Static RAMs
03/26/1999–LDS.174-M
TE
Latchup and static discharge protec-
tion are provided on-chip. The
L7C174 can withstand an injection
current of up to 200 mA on any pin
without damage.
L7C174
DEVICES INCORPORATED
8K x 8 Cache-Tag Static RAM
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2)
Storage temperature ............................................. –65°C to +150°C
Operating ambient temperature ............................ –55°C to +125°C
V
CC
supply voltage with
respect to ground ............................................... –0.5 V to +7.0 V
Input signal with respect to ground ....................... –3.0 V to +7.0 V
Signal applied to high
impedance output ............................................... –3.0 V to +7.0 V
Output current into low outputs ............................................. 25 mA
Latchup current ................................................................. > 200 mA
T
RUTH
T
ABLE
WE
X
X
H
H
H
L
CE
X
H
L
L
L
L
OE
X
X
H
H
L
X
CLEAR
L
H
H
H
H
H
MATCH
H
H
L
H
H
H
I/O
—
High-Z
D
IN
D
IN
D
OUT
D
IN
FUNCTION
Reset all bits to low
Deselect chip
No MATCH
MATCH
Read
Write
X = Don't Care; L = V
IL
; H = V
IH
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Industrial
Active Operation, Military
Data Retention, Commercial
Data Retention, Industrial
Data Retention, Military
Temperature Range
(Ambient)
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 5)
LE
35
90
2
Symbol
V
OH
V
OL
Parameter
Output High Voltage
(Note 11)
Output Low Voltage
(Note 11)
Test Condition
TE
Supply Voltage
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
2.0 V
≤
V
CC
≤
5.5 V
2.0 V
≤
V
CC
≤
5.5 V
2.0 V
≤
V
CC
≤
5.5 V
L7C174
Min
2.4
0.4
0.4
2.2
V
CC
+0.3
0.8
+10
+10
100
10
500
200
5
7
L7C174-
Typ
Max Unit
V
V
V
V
–3.0
–10
–10
V
µA
µA
µA
µA
pF
pF
25
115
20
140
15
165
12
195
Unit
mA
03/26/1999–LDS.174-M
V
CC
= 4.5 V,
I
OH
= –4.0 mA (all except MATCH pin)
I
OL
= 8.0 mA
(all except MATCH pin)
I
OL
= 18.0 mA
(MATCH pin)
V
IH
Input High Voltage
V
IL
I
IX
I
OZ
I
CC3
I
CC4
C
IN
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current, CMOS Standby
V
CC
Current, Data Retention
Input Capacitance
Output Capacitance
O
C
OUT
Symbol
I
CC1
Parameter
V
CC
Current, Active
BS
(Note 3)
(Note 8)
(Note 6)
O
Ground
≤
V
IN
≤
V
CC
Test Condition
Ground
≤
V
OUT
≤
V
CC,
OE =
V
CC
(except MATCH pin)
V
CC
= 3.0 V
(Notes 9, 10)
Ambient Temp = 25°C,
V
CC
= 5.0 V
Test Frequency = 1 MHz
(Note 10)
Special Architecture Static RAMs
L7C174
DEVICES INCORPORATED
8K x 8 Cache-Tag Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
MATCH
AND
CLEAR C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C174–
35
Symbol
t
AVAV
t
AVMV
t
AXMX
t
CLMV
t
CHMH
t
OLMH
t
WLMH
t
CLMH
t
DVMV
t
DXMX
t
CLCL
t
CLCH
t
CLIX
t
CLIR
Parameter
MATCH Cycle Time
Address Valid to MATCH Valid
Address Change to MATCH Change
Chip Enable Low to MATCH Valid
Chip Enable High to MATCH High
Output Enable Low to MATCH High
Write Enable Low to MATCH High
CLEAR Low to MATCH High
Data Valid to MATCH Valid
Data Change to MATCH Change
CLEAR Cycle Time
CLEAR Pulse Width
CLEAR Low to Inputs Don't Care
CLEAR Low to Inputs Recognized
0
65
20
0
3
3
3
0
25
20
3
20
3
3
Min
35
30
3
15
3
3
Max
25
Min
25
22
3
10
3
3
Max
20
Min
20
20
3
10
3
3
3
0
10
10
0
30
12
0
50
45
Max
Min
15
15
3
8
15
Max
12
Min
12
12
Max
LE
0
70
60
t
AVAV
t
CLMV
VALID MATCH DATA-IN
MATCH C
YCLE
ADDRESS
t
AVMV
CE
OE
O
VALID READ DATA-OUT
WE
CLEAR
BS
t
CLCH
t
CLIX
DATA
t
DVMV
MATCH VALID
MATCH
CLEAR C
YCLE
O
t
CLCL
t
CLIR
CLEAR
OE, WE
Special Architecture Static RAMs
3
03/26/1999–LDS.174-M
TE
3
3
3
0
20
0
15
0
12
15
15
13
0
0
0
55
45
35
15
15
0
50
12
0
t
AXMX
t
CHMH
t
OLMH
t
WLMH
t
CLMH
t
DXMX
L7C174
DEVICES INCORPORATED
8K x 8 Cache-Tag Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
R
EAD
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C174–
35
Symbol
t
AVAV
t
AVQV
t
AXQX
t
CLQV
t
CLQZ
t
CHQZ
t
OLQV
t
OLQZ
t
OHQZ
t
CHVL
Parameter
Read Cycle Time
Address Valid to Output Valid
(Notes 13, 14)
Address Change to Output Change
Chip Enable Low to Output Valid
(Notes 13, 15)
Chip Enable Low to Output Low Z
(Notes 20, 21)
Chip Enable High to Output High Z
(Notes 20, 21)
Output Enable Low to Output Valid
Output Enable Low to Output Low Z
(Notes 20, 21)
Output Enable High to Output High Z
(Notes 20, 21)
Chip Enable High to Data Retention
(Note 10)
0
0
12
3
15
15
3
15
3
10
Min
35
35
3
12
3
8
Max
25
Min
25
25
3
10
3
8
Max
20
Min
20
20
3
8
3
5
6
0
5
0
Max
Min
15
15
3
8
15
Max
12
Min
12
12
Max
R
EAD
C
YCLE
— A
DDRESS
C
ONTROLLED
Notes 13, 14
ADDRESS
t
AVQV
DATA OUT
PREVIOUS DATA VALID
t
AXQX
R
EAD
C
YCLE
— CE/OE C
ONTROLLED
Notes 13, 15
BS
t
CLQV
t
CLQZ
t
OLQZ
t
OLQV
HIGH IMPEDANCE
DATA RETENTION MODE
CE
O
t
AVAV
DATA VALID
4.5 V
4.5 V
≥
2V
LE
t
AVAV
t
AVAV
V
IH
4
OE
DATA OUT
O
D
ATA
R
ETENTION
Notes 9, 10
V
CC
t
CHVL
CE
V
IH
Special Architecture Static RAMs
03/26/1999–LDS.174-M
TE
12
10
8
0
0
0
10
8
5
0
0
0
DATA VALID
t
CHQZ
t
OHQZ
HIGH
IMPEDANCE
L7C174
DEVICES INCORPORATED
8K x 8 Cache-Tag Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
W
RITE
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C174–
35
Symbol
t
AVAV
t
CLEW
t
AVBW
t
AVEW
t
EWAX
t
WLEW
t
DVEW
t
EWDX
t
WHQZ
t
WLQZ
Parameter
Write Cycle Time
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Valid to End of Write Cycle
End of Write Cycle to Address Change
Write Enable Low to End of Write Cycle
Data Valid to End of Write Cycle
End of Write Cycle to Data Change
Write Enable High to Output Low Z
(Notes 20, 21)
Write Enable Low to Output High Z
(Notes 20, 21)
Min
25
25
0
25
0
20
15
0
0
10
Max
25
Min
20
15
0
15
0
15
Max
20
Min
20
15
0
15
0
15
Max
Min
15
12
0
12
0
12
7
15
Max
12
Min
12
10
0
10
0
10
6
0
0
4
Max
W
RITE
C
YCLE
— WE C
ONTROLLED
Notes 16, 17, 18
t
AVAV
ADDRESS
t
CLEW
CE
t
AVEW
WE
t
AVBW
DATA IN
LE
t
WLEW
t
DVEW
DATA-IN VALID
O
t
WLQZ
DATA OUT
HIGH IMPEDANCE
W
RITE
C
YCLE
— CE C
ONTROLLED
Notes 16, 17, 18
t
AVAV
t
CLEW
t
AVEW
t
WLEW
t
DVEW
DATA-IN VALID
ADDRESS
O
CE
BS
t
AVBW
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
Special Architecture Static RAMs
5
03/26/1999–LDS.174-M
TE
10
0
10
0
0
0
0
0
7
7
5
t
EWAX
t
EWDX
t
WHQZ
t
EWAX
t
EWDX
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