AT52BR3248-85CI datasheet, PDF

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AT52BR3248-85CI: DescriptionMemory Circuit, 2MX16, CMOS, PBGA66; Categorystorage storage; File Size346KB，44 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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AT52BR3248-85CI Overview

Memory Circuit, 2MX16, CMOS, PBGA66

AT52BR3248-85CI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microchip
package instruction	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66
Reach Compliance Code	unknow
Maximum access time	85 ns
Other features	SRAM IS ORGANISED AS 512K X 16
JESD-30 code	R-PBGA-B66
JESD-609 code	e0
length	11 mm
memory density	33554432 bi
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+SRAM
Number of functions	1
Number of terminals	66
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA66,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000002 A
Maximum slew rate	0.04 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

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Features

•

32-Mbit Flash and 4-Mbit/8-Mbit SRAM

•

Single 66-ball 8 mm x 11 mm CBGA Package

•

2.7V to 3.3V Operating Voltage

Flash

•

2.7V to 3.3V Read/Write

•

Access Time – 85, 90, 110 ns

•

Sector Erase Architecture

•

– Sixty-three 32K Word (64K Byte) Sectors with Individual Write Lockout

– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout

Fast Word Program Time – 20 µs

Fast Sector Erase Time – 200 ms

Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word and Fifteen 32K Word Sectors

Memory Plane B: Forty-eight 32K Word Sectors

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

Low-power Operation

– 25 mA Active

– 10 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Accelerated Program/Erase Operations

RESET Input for Device Initialization

Sector Lockdown Support

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

32-megabit

(2M x 16) Flash

+ 4-megabit

(256K x 16)/

8-megabit

(512K x 16)

SRAM

Stack Memory

AT52BR3244

AT52BR3244T

AT52BR3248

AT52BR3248T

SRAM

•

4-megabit (256K x 16)/8-megabit (512K x 16)

2.7V to 3.3V V

70 ns Access Time

Fully Static Operation and Tri-state Output

1.2V (Min) Data Retention

Industrial Temperature Range

Device Number

Flash Boot Location

Flash Plane

Architecture

SRAM Configuration

AT52BR3244

AT52BR3244T

AT52BR3248

AT52BR3248T

Bottom

Top

Bottom

Top

24M + 8M

256K x 16

512K x 16

Not Recommended for

New Designs. New

Designs Should Use

AT52BR3224(T)/3228(T)

Rev. 2471E–STKD–10/02

32-megabit Flash

Description

The 32-megabit Flash memory is organized as 2,097,152 words of 16 bits each or

4,194,304 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data

appears on I/O0 - I/O7. The memory is divided into 71 sectors for erase operations. The

device has CE and OE control signals to avoid any bus contention. This device can be

read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-

system programming.

The device powers on in the read mode. Command sequences are used to place the

device in other operation modes such as program and erase. The device has the capa-

bility to protect the data in any sector (see Sector Lockdown section).

The device is segmented into two memory planes. Reads from memory plane B may be

performed even while program or erase functions are being executed in memory plane

A and vice versa. This operation allows improved system performance by not requiring

the system to wait for a program or erase operation to complete before a read is per-

formed. To further increase the flexibility of the device, it contains an Erase Suspend

feature. This feature will put the erase on hold for any amount of time and let the user

read data from or program data to any of the remaining sectors within the same memory

plane. There is no reason to suspend the erase operation if the data to be read is in the

other memory plane. The end of a program or an erase cycle is detected by the

Ready/Busy pin, Data Polling or by the toggle bit.

The VPP pin provides faster program/erase times. With V

at 5.0V or 12.0V, the pro-

gram and erase operations are accelerated.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the

requirement of entering the three-byte program sequence is offered to further improve

programming time. After entering the six-byte code, only single pulses on the write con-

trol lines are required for writing into the device. This mode (Single Pulse Word

Program) is exited by powering down the device, or by pulsing the RESET pin low for a

minimum of 50 ns and then bringing it back to V

. Erase and Erase Suspend/Resume

commands will not work while in this mode; if entered they will result in data being pro-

grammed into the device. It is not recommended that the six-byte code reside in the

software of the final product but only exist in external programming code.

AT52BR3244(T)/3248(T)

2471E–STKD–10/02

AT52BR3248-85CI Related Products

	AT52BR3248-85CI	AT52BR3248T-85CI	AT52BR3248T-90CI	AT52BR3244-85CI	AT52BR3244T-11CI	AT52BR3244T-85CI	AT52BR3248-90CI	AT52BR3244-90CI
Description	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66	Memory Circuit, 2MX16, CMOS, PBGA66
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
package instruction	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66	11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CHIP SCALE, BGA-66
Reach Compliance Code	unknow	unknow	unknow	not_compliant	not_compliant	unknown	unknown	unknow
Maximum access time	85 ns	85 ns	90 ns	85 ns	110 ns	85 ns	90 ns	90 ns
Other features	SRAM IS ORGANISED AS 512K X 16	SRAM IS ORGANISED AS 512K X 16	SRAM IS ORGANISED AS 512K X 16	SRAM IS ORGANISED AS 256K X 16	SRAM IS ORGANISED AS 256K X 16	SRAM IS ORGANISED AS 256K X 16	SRAM IS ORGANISED AS 512K X 16	SRAM IS ORGANISED AS 256K X 16
JESD-30 code	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm
memory density	33554432 bi	33554432 bi	33554432 bi	33554432 bit	33554432 bit	33554432 bit	33554432 bit	33554432 bi
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	16	16	16	16	16	16	16	16
Mixed memory types	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	66	66	66	66	66	66	66	66
word count	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000	2000000	2000000	2000000	2000000	2000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	2MX16	2MX16	2MX16	2MX16	2MX16	2MX16	2MX16	2MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	LFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA66,8X12,32	BGA66,8X12,32	BGA66,8X12,32	BGA66,8X12,32	BGA68,8X12,32	BGA66,8X12,32	BGA66,8X12,32	BGA66,8X12,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240	240	240	240	240	NOT SPECIFIED	NOT SPECIFIED	240
power supply	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.4 mm	1.2 mm	1.2 mm	1.2 mm
Maximum standby current	0.000002 A	0.000002 A	0.000002 A	0.000002 A	0.000025 A	0.000002 A	0.000002 A	0.000002 A
Maximum slew rate	0.04 mA	0.04 mA	0.04 mA	0.04 mA	0.04 mA	0.04 mA	0.04 mA	0.04 mA
Maximum supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	NOT SPECIFIED	NOT SPECIFIED	30
width	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm
Maker	Microchip	Microchip	Microchip	-	Microchip	Microchip	Microchip	Microchip

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