Features
•
High-performance
– System Speeds > 100 MHz
– Flip-flop Toggle Rates > 250 MHz
– 1.2 ns/1.5 ns Input Delay
– 3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
Thousands of Registers
Cache Logic
®
Design
– Complete/Partial In-System Reconfiguration
– No Loss of Data or Machine State
– Adaptive Hardware
Low Voltage and Standard Voltage Operation
– 5.0 (V
CC
= 4.75V to 5.25V)
– 3.3 (V
CC
= 3.0V to 3.6V)
Automatic Component Generators
– Reusable Custom Hard Macro Functions
Very Low-power Consumption
– Standby Current of 500 µA/ 200 µA
– Typical Operating Current of 15 to 170 mA
Programmable Clock Options
– Independently Controlled Column Clocks
– Independently Controlled Column Resets
– Clock Skew Less Than 1 ns Across Chip
Independently Configurable I/O (PCI Compatible)
– TTL/CMOS Input Thresholds
– Open Collector/Tristate Outputs
– Programmable Slew-rate Control
– I/O Drive of 16 mA (combinable to 64 mA)
Easy Migration to Atmel Gate Arrays for High Volume Production
•
•
•
•
•
•
•
Coprocessor
Field
Programmable
Gate Arrays
AT6000(LV)
Series
•
•
Description
AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute-intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic
®
, which provides the
user with the ability to implement adaptive hardware and perform hardware
acceleration.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O.
(continued)
AT6000 Series Field Programmable Gate Arrays
Device
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
AT6002
6,000
1,024
1,024
96
15 - 30
32 x 32
AT6003
9,000
1,600
1,600
120
25 - 45
40 x 40
AT6005
15,000
3,136
3,136
108
40 - 80
56 x 56
AT6010
30,000
6,400
6,400
204
85 - 170
80 x 80
Rev. 0264F–10/99
1
Devices range in size from 4,000 to 30,000 usable gates,
and 1024 to 6400 registers. Pin locations are consistent
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
AT6000 Series FPGAs utilize a reliable 0.6 µm single-poly,
double-metal CMOS process and are 100% factory-tested.
Atmel's PC- and workstation-based Integrated Develop-
ment System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architecture was developed to provide the high-
est levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small size leads to arrays with large numbers of cells,
greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient commu-
nication over medium and long distances.
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array
of identical cells (Figure 1). The array is continuous and
completely uninterrupted from one edge to the other,
except for bus
repeaters
spaced every eight cells
(Figure 2).
In addition to logic and storage, cells can also be used as
wires to connect functions together over short distances
and are useful for routing in tight spaces.
The Busing Network
There are two kinds of buses: local and express (see
Figures 2 and 3).
Local buses are the link between the array of cells and the
busing network. There are two local buses – North-South 1
and 2 (NS1 and NS2) – for every column of cells, and two
local buses – East-West 1 and 2 (EW1 and EW2) – for
every row of cells. In a sector (an 8 x 8 array of cells
enclosed by repeaters) each local bus is connected to
every cell in its column or row, thus providing every cell in
the array with read/write access to two North-South and
two East-West buses.
Figure 1.
Symmetrical Array Surrounded by I/O
2
AT6000(LV) Series
AT6000(LV) Series
Figure 2.
Busing Network (one sector)
CELL
REPEATER
Figure 3.
Cell-to-cell and Bus-to-bus Connections
3
Each cell, in addition, provides the ability to route a signal
on a 90° turn between the NS1 bus and EW1 bus and
between the NS2 bus and EW2 bus.
Express buses are not connected directly to cells, and thus
provide higher speeds. They are the fastest way to cover
long, straight-line distances within the array.
Each express bus is paired with a local bus, so there are
two express buses for every column and two express
buses for every row of cells.
Connective units, called repeaters, spaced every eight
cells, divide each bus, both local and express, into
segments spanning eight cells. Repeaters are aligned in
rows and columns thereby partitioning the array into 8 x 8
sectors of cells. Each repeater is associated with a
local/express pair, and on each side of the repeater are
connections to a local-bus segment and an express-bus
segment. The repeater can be programmed to provide any
one of twenty-one connecting functions. These functions
are symmetric with respect to both the two repeater sides
and the two types of buses.
Among the functions provided are the ability to:
• Isolate bus segments from one another
• Connect two local-bus segments
• Connect two express-bus segments
• Implement a local/express transfer
In all of these cases, each connection provides signal
regeneration and is thus unidirectional. For bidirectional
connections, the basic repeater function for the NS2 and
EW2 repeaters is augmented with a special programmable
connection allowing bidirectional communication between
local-bus segments. This option is primarily used to imple-
ment long, tristate buses.
The Cell Structure
The Atmel cell (Figure 4) is simple and small and yet
can be programmed to perform all the logic and wiring
functions needed to implement any digital circuit. Its four
sides are functionally identical, so each cell is completely
symmetrical.
Read/write access to the four local buses – NS1, EW1,
NS2 and EW2 – is controlled, in part, by four bidirectional
pass gates connected directly to the buses. To read a local
bus, the pass gate for that bus is turned on and the three-
input multiplexer is set accordingly. To write to a local bus,
the pass gate for that bus and the pass gate for the associ-
ated tristate driver are both turned on. The two-input
multiplexer supplying the control signal to the drivers per-
mits either: (1) active drive, or (2) dynamic tristating
controlled by the B input. Turning between L
NS1
and L
EW1
or
between L
NS2
and L
EW2
is accomplished by turning on the
two associated pass gates. The operations of reading, writ-
ing and turning are subject to the restriction that each bus
can be involved in no more than a
single
operation.
Figure 4.
Cell Structure
4
AT6000(LV) Series
AT6000(LV) Series
In addition to the four local-bus connections, a cell receives
two inputs and provides two outputs to each of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B”. There is an A input and a B input from each neigh-
boring cell and an A output and a B output driving all four
neighbors. Between cells, an A output is always connected
to an A input and a B output to a B input.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers. Cell
flexibility is enhanced by allowing each multiplexer to select
also the logical constant “1”. The two multiplexer outputs
enter the two upstream AND gates.
Downstream from these two AND gates are an Exclusive-
OR (XOR) gate, a register, an AND gate, an inverter and
two four-input multiplexers producing the A and B outputs.
These multiplexers are controlled in tandem (unlike the
A and B input multiplexers) and determine the function of
the cell.
• In State 0 – corresponding to the “0” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s A output, and the output of
the right-hand upstream AND gate is connected to the
cell’s B output.
• In State 1 – corresponding to the “1” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
• In State 2 – corresponding to the “2” inputs of the
multiplexers – the XOR of the outputs from the two
upstream AND gates is provided to the cell’s A output,
while the NAND of these two outputs is provided to the
cell’s B output.
• In State 3 – corresponding to the “3” inputs of the
multiplexers – the XOR function of State 2 is provided to
the D input of a D-type flip-flop, the Q output of which is
connected to the cell’s A output. Clock and
asynchronous reset signals are supplied externally as
described later. The AND of the outputs from the two
upstream AND gates is provided to the cell's B output.
Logic States
The Atmel cell implements a rich and powerful set of logic
functions, stemming from 44 logical cell states which per-
mutate into 72 physical states. Some states use both A and
B inputs. Other states are created by selecting the “1” input
on either or both of the input multiplexers.
There are 28 combinatorial primitives created from the
cell’s tristate capabilities and the 20 physical states repre-
sented in Figure 5. Five logical primitives are derived from
the physical constants shown in Figure 7. More complex
functions are created by using cells in combination.
A two-input AND feeding an XOR (Figure 8) is produced
using a single cell (Figure 9). A two-to-one multiplexer
selects the logical constant “0” and feeds it to the right-
hand AND gate. The AND gate acts as a feed-through, let-
ting the B input pass through to the XOR. The three-to-one
multiplexer on the right side selects the local-bus input,
LNS1, and passes it to the left-hand AND gate. The A and
LNS1 signals are the inputs to the AND gate. The output of
the AND gate feeds into the XOR, producing the logic state
(A
l
L) XOR B.
5
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