AT6002LV-4JC datasheet, PDF - EEWORLD Datasheet

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AT6002LV-4JC: DescriptionS BAND, 1.2 pF, 60 V, SILICON, ABRUPT VARIABLE CAPACITANCE DIODE; CategoryProgrammable logic devices Programmable logic; File Size418KB，28 Pages; ManufacturerAtmel (Microchip)

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AT6002LV-4JC Overview

S BAND, 1.2 pF, 60 V, SILICON, ABRUPT VARIABLE CAPACITANCE DIODE

AT6002LV-4JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	LCC
package instruction	QCCJ, LDCC84,1.2SQ
Contacts	84
Reach Compliance Code	unknow
Other features	SRAM BASED
maximum clock frequency	166 MHz
Combined latency of CLB-Max	4 ns
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Humidity sensitivity level	2
Configurable number of logic blocks	1024
Equivalent number of gates	6000
Number of entries	64
Number of logical units	1024
Output times	64
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1024 CLBS, 6000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	29.3116 mm

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Features

•

High-performance

– System Speeds > 100 MHz

– Flip-flop Toggle Rates > 250 MHz

– 1.2 ns/1.5 ns Input Delay

– 3.0 ns/6.0 ns Output Delay

Up to 204 User I/Os

Thousands of Registers

Cache Logic

Design

– Complete/Partial In-System Reconfiguration

– No Loss of Data or Machine State

– Adaptive Hardware

Low Voltage and Standard Voltage Operation

– 5.0 (V

= 4.75V to 5.25V)

– 3.3 (V

= 3.0V to 3.6V)

Automatic Component Generators

– Reusable Custom Hard Macro Functions

Very Low-power Consumption

– Standby Current of 500 µA/ 200 µA

– Typical Operating Current of 15 to 170 mA

Programmable Clock Options

– Independently Controlled Column Clocks

– Independently Controlled Column Resets

– Clock Skew Less Than 1 ns Across Chip

Independently Configurable I/O (PCI Compatible)

– TTL/CMOS Input Thresholds

– Open Collector/Tristate Outputs

– Programmable Slew-rate Control

– I/O Drive of 16 mA (combinable to 64 mA)

Easy Migration to Atmel Gate Arrays for High Volume Production

•

Coprocessor

Field

Programmable

Gate Arrays

AT6000(LV)

Series

•

Description

AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for

use as reconfigurable coprocessors and implementing compute-intensive logic.

Supporting system speeds greater than 100 MHz and using a typical operating current

of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive

designs. These FPGAs are designed to implement Cache Logic

, which provides the

user with the ability to implement adaptive hardware and perform hardware

acceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yet

powerful cells connected to a flexible busing network. Independently controlled clocks

and resets govern every column of cells. The array is surrounded by programmable

I/O.

(continued)

AT6000 Series Field Programmable Gate Arrays

Device

Usable Gates

Cells

Registers (maximum)

I/O (maximum)

Typ. Operating Current (mA)

Cell Rows x Columns

AT6002

6,000

1,024

15 - 30

32 x 32

AT6003

9,000

1,600

120

25 - 45

40 x 40

AT6005

15,000

3,136

108

40 - 80

56 x 56

AT6010

30,000

6,400

204

85 - 170

80 x 80

Rev. 0264F–10/99

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