ZL40231LDG1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> ZL40231LDG1

ZL40231LDG1: DescriptionClock Driver; Categorylogic logic; File Size2MB，36 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

Download Datasheet Parametric Compare View All

ZL40231LDG1 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	ZL40231LDG1	-	-	View	Buy Now

ZL40231LDG1 Overview

Clock Driver

ZL40231LDG1 Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	QFN-48
Reach Compliance Code	compli
Factory Lead Time	8 weeks
Other features	HAS ULTRA-LOW ADDITIVE JITTER LVCMOS OUTPUT; ALSO OPERATES AT 3.3 V SUPPLY
series	4000/14000/40000
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N48
length	7 mm
Load capacitance (CL)	1 pF
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	48
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC48,.27SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TR
Maximum supply current (ICC)	197 mA
propagation delay (tpd)	2.3 ns
Same Edge Skew-Max（tskwd）	0.04 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm
minfmax	1600 MHz

Preview

Download Datasheet

View All

Data Sheet

ZL40231

Low Skew, Low Additive Jitter, 10 output LVPECL/LVDS/HCSL

Fanout Buffer with one LVCMOS output

Features

•

3 to 1 input Multiplexer: Two inputs accept any

differential (LVPECL, HCSL, LVDS, SSTL, CML,

LVCMOS) or a single ended signal and the third

input accepts a crystal or a single ended signal

•

Ten differential LVPECL/LVDS/HCSL outputs

•

One LVCMOS output

•

Ultra-low additive jitter: 24fs (integration band:

12kHz to 20MHz at 625MHz clock frequency)

•

Supports clock frequencies from 0 to 1.6GHz

•

Supports 2.5V or 3.3V power supplies on LVPECL,

LVDS or HCSL outputs

•

Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS

outputs

•

Embedded Low Drop Out (LDO) Voltage regulator

provides superior Power Supply Noise Rejection

•

Maximum output to output skew of 40ps

•

Device controlled via control pins

OUTA_TYPE_SEL0

OUTA_TYPE_SEL1

OUT_A_TYPE_SEL[1:0] BANK A OUTPUT

LVECL

LVDS

HCSL

HIGH-Z

Ordering Information

ZL40231LDG1

ZL40231LDF1

48 Pin QFN

48 pin QFN

Trays

Tape and Reel

Package size: 7 x 7 mm

-40



C to +85



-40



C to +85



Applications

•

General purpose clock distribution

Low jitter clock trees

Logic translation

Clock and data signal restoration

Wired communications: OTN, SONET/SDH, GE, 10 GE,

FC and 10G FC

PCI Express generation 1/2/3/4 clock distribution

Wireless communications

High performance microprocessor clock distribution

Test Equipment

Bank A

OUT0_p

OUT0_n

OUT1_p

OUT1_n

IN_SEL0

IN_SEL1

IN0_p

IN0_n

IN1_p

IN1_n

Bank B

OUT2_p

OUT2_n

OUT3_p

OUT3_n

OUT4_p

OUT4_n

XOUT

ZL40231

OUT5_p

OUT5_n

XIN

OUT6_p

OUT6_n

OUT7_p

OUT7_n

OUT8_p

OUT8_n

OUT_B_TYPE_SEL[1:0] BANK B OUTPUT

LVECL

LVDS

HCSL

HIGH-Z

OUTB_TYPE_SEL0

OUTB_TYPE_SEL1

Synchronous

OUT9_p

OUT9_n

LVCMOS_OE

OUT10

Figure 1. Functional Block Diagram

October 2018

ZL40231

Data Sheet

ZL40231

Table of Contents

Features ..................................................................................................................................... 1

Applications................................................................................................................................ 1

Table of Contents ...................................................................................................................... 2

Pin Diagram ............................................................................................................................... 5

Pin Descriptions ......................................................................................................................... 6

Functional Description ............................................................................................................... 9

Clock Inputs ............................................................................................................................... 9

Clock Outputs .......................................................................................................................... 12

Crystal Oscillator Input ............................................................................................................. 13

Termination of unused inputs and outputs .............................................................................. 13

Power Consumption ................................................................................................................ 13

Power Supply Filtering ............................................................................................................. 14

Power Supplies and Power-up Sequence ............................................................................... 14

Host Interface .......................................................................................................................... 15

Typical device performance ..................................................................................................... 16

AC and DC Electrical Characteristics ...................................................................................... 20

Absolute Maximum Ratings ..................................................................................................... 20

Recommended Operating Conditions ..................................................................................... 20

Change History ........................................................................................................................ 34

Package Outline ...................................................................................................................... 35

October 2018

ZL40231

Data Sheet

ZL40231

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Figure 38.

Functional Block Diagram ........................................................................................................................................... 1

Pin Diagram ................................................................................................................................................................ 5

Input driven by a single ended output ........................................................................................................................ 9

Input driven by DC coupled LVPECL output ................................................................................................................. 9

Input driven by DC coupled LVPECL output (alternative termination) ...................................................................... 10

Input driven by AC coupled LVPECL output ............................................................................................................... 10

Input driven by HCSL output ..................................................................................................................................... 10

Input driven by LVDS output ..................................................................................................................................... 11

Input driven by AC coupled LVDS .............................................................................................................................. 11

Input driven by an SSTL output ................................................................................................................................. 11

Termination for LVCMOS output .............................................................................................................................. 12

Driving a load via transformer .................................................................................................................................. 12

Crystal Oscillator Circuit............................................................................................................................................ 13

Power Supply Filtering .............................................................................................................................................. 14

156.25MHz LVPECL ................................................................................................................................................... 16

1.5GHz LVPECL .......................................................................................................................................................... 16

156.25MHz LVDS ...................................................................................................................................................... 16

1.5GHz LVDS ............................................................................................................................................................. 16

100MHz HCSL............................................................................................................................................................ 16

250MHz HCSL............................................................................................................................................................ 16

I/O delay vs temperature .......................................................................................................................................... 17

PSNR vs noise frequency ........................................................................................................................................... 17

100MHz LVPECL Phase Noise ................................................................................................................................... 17

100MHz LVDS Phase Noise ....................................................................................................................................... 17

25MHz LVDS Phase Noise in Xtal mode .................................................................................................................... 17

100MHz HCSL Phase Noise ....................................................................................................................................... 17

156.25MHz LVPECL Phase Noise............................................................................................................................... 18

625MHz LVPECL Phase Noise .................................................................................................................................... 18

156.25MHz LVDS Phase Noise .................................................................................................................................. 18

625MHz LVDS Phase Noise ....................................................................................................................................... 18

Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 19

Output clock noise floor vs input clock slew-rate ..................................................................................................... 19

Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 19

Output clock noise floor vs input clock slew-rate ..................................................................................................... 19

Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 19

Output clock noise floor vs input clock slew-rate ..................................................................................................... 19

Differential Input Voltage Levels .............................................................................................................................. 21

Differential Output Voltage Levels ........................................................................................................................... 25

October 2018

ZL40231

Data Sheet

ZL40231

List of Tables

Table 1 Pin Descriptions ................................................................................................................................................................................. 6

Table 2 Input clock selection ........................................................................................................................................................................ 15

Table 3 Output Type Selection ...................................................................................................................................................................... 15

Table 4 Absolute Maximum Ratings* ........................................................................................................................................................... 20

Table 5 Recommended Operating Conditions* ............................................................................................................................................ 20

Table 6 Current consumption ....................................................................................................................................................................... 20

Table 7 Input Characteristics* ...................................................................................................................................................................... 21

Table 8 Crystal Oscillator Characteristics* ................................................................................................................................................... 22

Table 9 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* .................................................................................................................. 22

Table 10 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* ................................................................................................................ 23

Table 11 LVCMOS Output Characteristics for VDDO = 3.3V* ....................................................................................................................... 23

Table 12 LVCMOS Output Characteristics for VDDO = 2.5V* ....................................................................................................................... 24

Table 13 LVPECL Output Characteristics for VDDO = 3.3V* ......................................................................................................................... 25

Table 14 LVPECL Output Characteristics for VDDO = 2.5V* ......................................................................................................................... 26

Table 15 LVDS Outputs for VDDO = 3.3V* .................................................................................................................................................... 27

Table 16 LVDS Outputs for VDDO = 2.5V* .................................................................................................................................................... 28

Table 17 HCSL Outputs for VDDO = 3.3V* .................................................................................................................................................... 29

Table 18 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 30

Table 19 LVCMOS Output Phase Noise with 25 MHz XTAL*......................................................................................................................... 31

Table 20 LVPECL Output Phase Noise with 25 MHz XTAL* ........................................................................................................................... 31

Table 21 LVDS Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 32

Table 22 HCSL Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 32

Table 23 7x7mm QFN Package Thermal Properties ..................................................................................................................................... 33

October 2018

ZL40231

ZL40231LDG1 Related Products

	ZL40231LDG1	ZL40231LDF1
Description	Clock Driver	Clock Driver
Maker	Microchip	Microchip
package instruction	QFN-48	QFN-48
Reach Compliance Code	compli	compli
Factory Lead Time	8 weeks	8 weeks
Other features	HAS ULTRA-LOW ADDITIVE JITTER LVCMOS OUTPUT; ALSO OPERATES AT 3.3 V SUPPLY	HAS ULTRA-LOW ADDITIVE JITTER LVCMOS OUTPUT; ALSO OPERATES AT 3.3 V SUPPLY
series	4000/14000/40000	4000/14000/40000
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N48	S-XQCC-N48
length	7 mm	7 mm
Load capacitance (CL)	1 pF	1 pF
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	1	1
Number of terminals	48	48
Actual output times	10	10
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC48,.27SQ,20	LCC48,.27SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TR	TRAY
Maximum supply current (ICC)	197 mA	197 mA
propagation delay (tpd)	2.3 ns	2.3 ns
Same Edge Skew-Max（tskwd）	0.04 ns	0.04 ns
Maximum seat height	1 mm	1 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
width	7 mm	7 mm
minfmax	1600 MHz	1600 MHz

Recommended Resources

Multifunctional environmentally friendly circuit

Wiring to suppress microcomputer power grid interference with low-pass filter

Sleepy notification circuit

Output protection circuit

bridge circuit

Push-pull power amplifier circuit

Problems with creating txt file system for pic microcontroller: I used the file system compiled by pic chip to create a txt file and write a string into it. I referred to the 51 program of Zhennan znfat. But now the created file cannot be displayed on the computer...; guang_84 Microchip MCU

Is this MOS tube drawn wrong?: [i=s]This post was last edited by jishuaihu on 2015-5-22 13:27[/i] Is this MOS tube drawn wrong? As shown in the figure, the function of the circuit is also explained. When looking at this figure, I f...; jishuaihu Integrated technical exchanges

Hercules DIY Week 5 (Content is incorrect): [font=Helvetica, Arial, sans-serif][size=12px]Sorry, I didn't mean to post the post I submitted in the fifth week, but I made some mistakes. I am revising it recently. But thank you all the same!! The...; Sur Microcontroller MCU

How to modify the project name in evc: I want to change the name of an existing evc project without affecting the normal operation of the project. What should I do? Thank you!...; berryfan Embedded System

High fanout solution: Fanout is the number of lower-level modules directly called by a module. If this value is too large, it will directly manifest as a large net delay in the FPGA, which is not conducive to timing conver...; eeleader FPGA/CPLD

When TMR2≥CCPR1L, the PWM function pin starts to output a low level.: When TMR2≥CCPR1L, the PWM function pin starts to output a low level.When TMR2≥PR2, TMR2=0, another cycle count starts again, and the PWM function pin starts to output a high level. How do I write thes...; a372708078 Microchip MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components