DATA SHEET
1G bits GDDR5 SGRAM
EDW1032BABG (32M words x 32 bits)
Specifications
• Density: 1G bits
• Organization
— 2Mbit x 32 I/O x 16 banks
— 4Mbit x 16 I/O x 16 banks
• Package
— 170-ball FBGA
— Lead-free (RoHS compliant) and Halogen-free
• Power supply:
— VDD: 1.5V ±3% and 1.35V ± 3%
— VDDQ: 1.5V ±3% and 1.35V ±3%
• Data rate: 6.0Gbps/5.0Gbps/4.0Gbps (max.)
• 16 internal banks
• Four bank groups for tCCDL = 3tCK
• 8n prefetch architecture: 256 bit per array Read or
Write access
• Burst length (BL): 8 only
• Programmable CAS latency: 6 to 20
• Programmable Write latency: 3 to 7
• Programmable CRC READ latency: 0 to 3
• Programmable CRC WRITE latency: 8 to 14
• Programmable EDC hold pattern for CDR
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/32ms
• Interface: Pseudo open drain (POD-15)
• On-die termination (ODT): nom. values of 60Ω or 120Ω
• Pseudo open drain (POD-15) compatible outputs
— 40Ω pulldown
— 60Ω pullup
• ODT and output driver strength auto-calibration with
external resistor ZQ pin (120Ω)
• Programmable termination and driver strength offsets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address / command inputs
• Operating case temperature range
— TC = 0°C to +95°C
Features
• x32/x16 mode configuration set at power-up with
EDC pin
• Single ended interface for data, address and command
• Quarter data-rate differential clock inputs CK, /CK for
address and commands
• Two half data-rate differential clock inputs WCK, /WCK,
each associated with two data bytes (DQ, /DBI, EDC)
• Double Data Rate (DDR) data (WCK)
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR) addressing (CK)
• Write data mask function via address bus
(single/double byte mask)
• Data Bus Inversion (DBI) and Address Bus Inversion
(ABI)
• Input/output PLL on/off mode
• Address training: address input monitoring via DQ pins
• WCK2CK clock training: phase information via EDC
pins
• Data read and write training via Read FIFO (FIFO
depth = 6)
• Read FIFO pattern preload by LDFF command
• Direct write data load to Read FIFO by WRTR
command
• Consecutive read of Read FIFO by RDTR command
• Read/Write data transmission integrity secured by
cyclic redundancy check (CRC–8)
• Read/Write EDC on/off mode
• DQ Preamble for Read on/off mode
• Low Power modes
• RDQS mode on EDC pin
• On-chip temperature sensor with read-out
• Automatic temperature sensor controlled self-refresh
rate
• Digital tRAS lockout
• Vendor ID, FIFO depth and Density info fields for
identification
• Mirror function with MF pin
• Boundary Scan function with SEN pin
Document No. E1597E20 (Ver. 2.0)
Date Published
June
2010 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©
Elpida Memory, Inc. 2009-2010
EDW1032BABG
1.
Configuration
The Elpida GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring
high bandwidth. It contains 1,073,741,824 bits and is internally configured as a 16-bank DRAM.
The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. The
device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device
initialization. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins.
Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CK clock cycle data
transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers
at the I/O pins.
The GDDR5 SGRAM operates from a differential clock CK and /CK. Commands are registered at every rising edge
of CK. Addresses are registered at every rising edge of CK and every rising edge of /CK.
GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running
differential forwarded clock (WCK, /WCK) with both input and output data registered and driven respectively at both
edges of the forwarded WCK.
Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and
continues for a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and
the next rising /CK edge are used to select the bank and the row to be accessed. The address bits registered
coincident with the READ or WRITE command and the next rising /CK edge are used to select the bank and the
column location for the burst access.
Data Sheet E1597E20 (Ver. 2.0)
5
Microchip MCU
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