Features
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Utilizes the AVR
®
Enhanced RISC Architecture
AVR - High Performance and Low Power RISC Architecture
118 Powerful Instructions - Most Single Clock Cycle Execution
8K bytes of In-System Programmable Flash AT90S/LS8535
4K bytes of In-System Programmable Flash AT90S/LS4434
– SPI Serial Interface for In-System Programming
– Endurance: 1,000 Write/Erase Cycles
512 bytes EEPROM AT90S/LS8535
256 bytes EEPROM AT90S/LS4434
– Endurance: 100,000 Write/Erase Cycles
512 bytes Internal SRAM AT90S/LS8535
256 bytes Internal SRAM AT90S/LS4434
8-Channel, 10-Bit ADC
32 x 8 General Purpose Working Registers
32 Programmable I/O Lines
Programmable Serial UART
V
CC
: 4.0 - 6.0V AT90S4434/AT90S8535
V
CC
: 2.7 - 6.0V AT90LS4434/AT90LS8535
Speed Grades:
0 - 8 MHz AT90S4434/AT90S8535,
0 - 4 MHz (AT90LS4434/AT90LS8535
Power-On Reset Circuit
Up to 8 MIPS Throughput at 8 MHz
RTC with Separate Oscillator and Counter Mode
Two 8-Bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes
3 PWM channels
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
On-Chip Analog Comparator
Three Sleep Modes: Idle, Power Save, and Power Down
Programming Lock for Software Security
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8-Bit
Microcontroller
with 4K/8K
Bytes In-System
Programmable
Flash
AT90S4434
AT90LS4434
AT90S8535
AT90LS8535
Advance
Information
Description
The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR
®
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing
speed.
(continued)
Pin Configurations
Rev. 1041AS–05/98
Note: This is a summary document. For the complete 80 page
document, please visit our website at
www.atmel.com
or e-mail at
1
literature@atmel.com
and request literature #1041A.
Block Diagram
PA0 - PA7
PC0 - PC7
VCC
PORTA DRIVERS
PORTC DRIVERS
GND
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
ANALOG MUX
AGND
AREF
ADC
OSCILLATOR
XTAL1
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
XTAL2
RESET
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
UART
ANALOG
COMPARATOR
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
+
-
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD7
The AVR core combines a rich instruction set with 32 gen-
eral purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving through-
puts up to ten times faster than conventional CISC micro-
controllers.
The AT90S4434/8535 provides the following features:
4K/8K bytes of In-System Programmable Flash, 256/512
bytes EEPROM, 256/512 bytes SRAM, 32 general purpose
I/O lines, 32 general purpose working registers, RTC, three
flexible timer/counters with compare modes, internal and
external interrupts, a programmable serial UART, 8-chan-
nel, 10-bit ADC, programmable Watchdog Timer with inter-
nal oscillator, an SPI serial port and three software
selectable power saving modes. The Idle mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The Power
Down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power Save mode, the timer
oscillator continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high density
non-volatile memory technology. The on-chip ISP Flash
2
AT90S/LS4434 and AT90S/LS8535
AT90S/LS4434 and AT90S/LS8535
allows the program memory to be reprogrammed in-system
through an SPI serial interface or by a conventional nonvol-
atile memory programmer. By combining an 8-bit RISC
CPU with In-System Programmable Flash on a monolithic
chip, the Atmel AT90S4434/8535 is a powerful microcon-
troller that provides a highly flexible and cost effective solu-
tion to many embedded control applications.
The AT90S4434/8535 AVR is supported with a full suite of
program and system development tools including: C com-
pilers, macro assemblers, program debugger/simulators,
in-circuit emulators, and evaluation kits.
Comparison between AT90S4434 and AT90S8535
The AT90S4434 has 4K bytes of In-System Programmable
Flash, 256 bytes of EEPROM, and 256 bytes of internal
SRAM.
The AT90S8535 has 8K bytes of In-System Programmable
Flash, 512 bytes of EEPROM, and 512 bytes of internal
SRAM.
Table 1 summarizes the different memory sizes for the two
devices.
Table 1.
Memory Size Summary
Part
AT90S4434
AT90S8535
Flash
4K bytes
8K bytes
EEPROM
256 bytes
512 bytes
SRAM
256 bytes
512 bytes
Pin Descriptions
VCC
Digital supply voltage
GND
Digital ground
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can pro-
vide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED dis-
plays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port A also serves as the analog inputs to the A/D Con-
verter.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features
of the AT90S4434/8535 as listed on page 52.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pullup
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. Two Port C
pins can alternatively be used as oscillator for
Timer/Counter2.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features
of the AT90S4434/8535 as listed on page 59.
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
AVCC
This is the supply voltage pin for the A/D Converter. It
should be externally connected to VCC via a low-pass filter.
See page 47 for details on operation of the ADC.
AREF
This is the analog reference input for the A/D Converter.
For ADC operations, a voltage in the range AGND to AV
CC
must be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground
plane, this pin should be connected to this ground plane.
Otherwise, connect to GND.
Crystal Oscillators
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
For the Timer Oscillator pins, PC6(OSC1) and PC7(OSC2),
the crystal is connected directly between the pins. No
external capacitors are needed. The oscillator is optimized
for use with a 32,768 Hz watch crystal. An external clock
signal applied to this pin goes through the same amplifier
having a bandwidth of 256 kHz. The external clock signal
should therefore be in the interval 0 Hz - 256 kHz.
3
Figure 1.
Oscillator Connections
Figure 2.
External Clock Drive Configuration
Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one Arithmetic Logic Unit (ALU) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect
address register pointers for Data Space addressing -
enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function reg-
isters are the 16-bits X-register, Y-register and Z-register.
Figure 3.
The AT90S4434/8535
AVR
Enhanced RISC Architecture
AVR
AT90S4434/8535 Architecture
Data Bus 8-bit
2K/4K X 16
Program
Memory
Program
Counter
Status
and Control
Interrupt
Unit
SPI
Unit
Serial
UART
8-bit
Timer/Counter
Instruction
Register
32 x 8
General
Purpose
Registrers
Indirect Addressing
Instruction
Decoder
Direct Addressing
ALU
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog to Digital
Converter
Analog
Comparator
Control Lines
256/512 x 8
Data
SRAM
256/512 x 8
EEPROM
32
I/O Lines
4
AT90S/LS4434 and AT90S/LS8535
AT90S/LS4434 and AT90S/LS8535
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 3
shows the AT90S4434/8535 AVR Enhanced RISC micro-
controller architecture.
In addition to the register operation, the conventional mem-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept
Figure 4.
Memory Maps
Program Memory
$000
Data Memory
32 Gen. Purpose $0000
Working Registers $001F
$0020
64 I/O Registers
Program Flash
(2K/4K x 16)
$005F
$0060
EEPROM
(256/512 x 8)
enables instructions to be executed in every clock cycle.
The program memory is in-system downloadable Flash
memory.
With the relative jump and call instructions, the whole
2K/4K address space is directly accessed. Most AVR
instructions have a single 16-bit word format. Every pro-
gram memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 9-bit stack pointer SP is read/write
accessible in the I/O space.
The 256/512 bytes data SRAM can be easily accessed
through the five different addressing modes supported in
the AVR architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
Data Memory
$0000
Internal SRAM
(256/512 x 8)
$1F/$FF
$015F/$025F
$7FF/$FFF
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