EEWORLDEEWORLDEEWORLD

Part Number

Search

TRU050-TDCNB-47M4570000

Description
Phase Locked Loop, CDIP16, SMD-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size427KB,14 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
Download Datasheet Parametric View All

TRU050-TDCNB-47M4570000 Overview

Phase Locked Loop, CDIP16, SMD-16

TRU050-TDCNB-47M4570000 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrosemi
package instructionSMD-16
Reach Compliance Codecompli
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
JESD-30 codeR-CDIP-T16
JESD-609 codee4
length20.32 mm
Humidity sensitivity level1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height4.69 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
Temperature levelCOMMERCIAL
Terminal surfaceGold (Au) - with Nickel (Ni) barrie
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.62 mm
TRU050
Complete VCXO based Phase-Locked Loop
Features
Output Frequencies to 65.536 MHz
5.0 V or 3.3Vdc Operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS Outputs
0/70° or –40/85° Temperature Range
C
Ceramic SMD Package
RoHS/Lead Free Compliant Versions
The TRU050, VCXO based PLL
Description
The VI TRU050 is a user-configurable crystal-based
PLL integrated circuit. It includes a digital phase
detector, op-amp, VCXO and additional integrated
functions for use in digital synchronization
applications. Loop filter software is available as well
SPICE models for circuit simulation.
Applications
Frequency Translation
Clock Smoothing
NRZ Clock Recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low Jitter PLL’s
Figure 1. TRU050 Block Diagram
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 1 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev:
4/12/2016
EEWORLD University ---- Mingdeyang FPGA learning video
Mingdeyang FPGA learning video : https://training.eeworld.com.cn/course/587...
shaoyuan02 FPGA/CPLD
Help with DSP chip BE control line problem
Hello, when I was debugging DSP (6701), I found that when the program was downloaded to SDRAM, it could only run according to INT data. If it was read and written according to bytes, it would be chaot...
xiaoxi8592 DSP and ARM Processors
nios exchange group
nios communication! Group number: 62099724! Those who do not communicate for a long time will be kicked out of the group!...
天地容我心 FPGA/CPLD
Who knows this digital tube?
I want to know the pin parameters of this digital tube. Does anyone know?...
zk643 Analog electronics
Zhuhai Allianz Ruishi Technology Co., Ltd. is recruiting
Embedded Software Engineers (ARM) 2 persons aged 23-35, college degree or above, major in computer or electronics, more than two years of experience in embedded development, proficient in C/C++, famil...
liguohua1985 Embedded System
[Sample code] AD5143 usage code
>>...
nmg ADI Reference Circuit

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 768  2779  2856  1937  2521  16  56  58  40  51 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号