82C836 datasheet, PDF - EEWORLD Datasheet

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82C836: DescriptionSingle-Chip 386sx AT; File Size4MB，205 Pages; ManufacturerETC1

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82C836 Overview

Single-Chip 386sx AT

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82C836

CHIPSet

Single-Chip 386sx AT

Data Sheet

March 1993

Contents

Section 1

82C836 CHIPSet Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

1-2

Section 2

Pin Assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

2-2

2-9

Section 3

Functional Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Battery Backup and Power-Up/Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Standby Power Management and Laptop Support . . . . . . . . . . . . . . . . . . . . . . . . . .

Operational Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-3

3-5

3-6

Section 4

Clock/Bus Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Reset and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Control Arbitration and Basic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

4-2

4-3

Section 5

System Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ROM/Shadow RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCATsx Memory Address Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCATsx Memory Bank Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Memory Configuration Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .

Support for External Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Expanded/Extended Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Numeric Coprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Keyboard Controller Interface ----External 8042 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

5-2

5-9

5-10

5-12

5-14

5-16

5-18

Chips and Technologies, Inc.

PRELIMINARY

Revision 3.0

Contents

82C836 CHIPSet Data Sheet

Section 6

Real Time Clock and Interval Timer Registers

. . . . . . . . . . . . . . . . . . . . . . . . .

Real Time Clock Interface ----MC146818 Compatible . . . . . . . . . . . . . . . . . . . . . .

Real Time Clock Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Update Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interval Timer ----8254 Compatible . . . . . . . . . . . . . . . . . . . . . . . . .

Counter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming the Counter Timer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read/Write Counter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Latch Counter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read-Back Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1

6-2

6-4

6-7

6-9

6-10

6-11

6-12

6-13

6-14

6-15

6-17

Section 7

Interrupt Controller

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

End-Of-Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Priority Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fixed Priority Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specific Rotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Rotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming the Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization Command Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operational Command Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-1

7-3

7-4

7-5

7-6

7-7

7-8

7-12

Section 8

DMA Controller

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Idle Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Program Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Active Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DREQ Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Compressed Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1

8-3

8-4

8-6

8-7

8-8

Revision 3.0

PRELIMINARY

Chips and Technologies, Inc.

82C836 CHIPSet Data Sheet

Contents

DMA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current Word Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Base Word Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Request Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Temporary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-9

8-10

8-12

8-13

8-15

8-16

Section 9

Address Maps

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-1

9-6

Section 10

Configuration Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMS Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-1

10-16

Section 11

System Timing Relationships

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU Access to AT-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-MEMCS16 and -IOCS16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IOCHRDY and OWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-NA/-STCYC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-CAS Only DRAM Access by CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Local DRAM Bank Switch (SRA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Wait State Page Miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cache Mode Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Early READY and LBA Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRQ/DACK Scanning in MRA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA and Master Access to Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Refresh (HLDA and 14MHz-Based) . . . . . . . . . . . . . . . . . . . . . . . . . .

Hidden Refresh (PROCCLK-Based, No HLDA) . . . . . . . . . . . . . . . . . . . . . . . .

Standby Refresh (32KHz-Based) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Turn-On and System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-1

11-6

11-8

11-9

11-10

11-12

11-14

11-16

11-18

11-19

11-20

11-24

11-26

11-27

11-30

11-32

11-34

Chips and Technologies, Inc.

PRELIMINARY

Revision 3.0

vii

82C836 Related Products

	82C836	82C836A	82C836A-16	82C836A-20	82C836B
Description	Single-Chip 386sx AT	Single-Chip 386sx AT	Single-Chip 386sx AT	Single-Chip 386sx AT	Single-Chip 386sx AT

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