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ATF1502AS-10QC44

Description
High Performance E2PROM CPLD
CategoryProgrammable logic devices    Programmable logic   
File Size251KB,18 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

ATF1502AS-10QC44 Overview

High Performance E2PROM CPLD

ATF1502AS-10QC44 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAtmel (Microchip)
Parts packaging codeQFP
package instructionQFP, QFP44,.5SQ,32
Contacts44
Reach Compliance Codecompli
Other featuresYES
maximum clock frequency125 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G44
JESD-609 codee0
JTAG BSTYES
length10 mm
Dedicated input times
Number of I/O lines32
Number of macro cells32
Number of terminals44
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 32 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP44,.5SQ,32
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)240
power supply3.3,5 V
Programmable logic typeEE PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height2.45 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width10 mm
Features
High Density, High Performance Electrically Erasable Complex Programmable Logic
Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 pin
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register with a COM output
Advanced Power Management Features
– Automatic 3 mA Stand-By for “L” Version
– Pin-Controlled 4 mA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-pin PLCC; TQFP; and PQFP
Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
High
Performance
E
2
PROM CPLD
ATF1502AS
Preliminary
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D - Latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-Keeper” Option
V
CC
Power-Up Reset Option
Pull-Up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge Controlled Power Down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0995A–04/98
1
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