P5021NSN7VNB datasheet, PDF - EEWORLD Datasheet

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P5021NSN7VNB: DescriptionRISC PROCESSOR; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，155 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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P5021NSN7VNB Overview

RISC PROCESSOR

P5021NSN7VNB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
package instruction	BGA,
Reach Compliance Code	compli
ECCN code	3A991
Address bus width	16
boundary scan	YES
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B1295
JESD-609 code	e1
length	37.5 mm
low power mode	YES
Number of terminals	1295
Maximum operating temperature	105 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	3.53 mm
speed	2000 MHz
Maximum supply voltage	1.15 V
Minimum supply voltage	1.05 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	37.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: P5021

Rev. 1, 05/2014

P5021

P5021 QorIQ

Integrated Processor

Data Sheet

The P5021 QorIQ integrated communication processor

combines two Power Architecture® processor cores with

high-performance data path acceleration logic and network

and peripheral bus interfaces required for networking,

telecom/datacom, wireless infrastructure, and aerospace

applications.

This chip can be used for combined control, data path, and

application layer processing in routers, switches, base station

controllers, and general-purpose embedded computing. Its

high level of integration offers significant performance

benefits compared to multiple discrete devices while also

greatly simplifying board design.

The chip includes the following function and features:

• Two e5500 Power Architecture cores

– Each core has a backside 512 KB L2 cache with ECC

– Three levels of instructions: user, supervisor, and

hypervisor

– Independent boot and reset

– Secure boot capability

• CoreNet fabric supporting coherent and non-coherent

transactions amongst CoreNet endpoints

• Frontside 2 MB CoreNet platform cache with ECC

• CoreNet bridges between the CoreNet fabric the I/Os,

datapath accelerators, and high and low speed peripheral

interfaces

• Two 10-Gigabit Ethernet (XAUI) controllers

• Ten 1-Gigabit Ethernet controllers

– SGMII, 2.5Gb/s SGMII and RGMII interfaces

• Two 64-bit DDR3/3L SDRAM memory controllers with

ECC

• Multicore programmable interrupt controller (PIC)

• Four I

C controllers

• Four 2-pin UARTs or two 4-pin UARTs

• Two 4-channel DMA engines

• Enhanced local bus controller (eLBC)

• Three PCI Express 2.0 controllers/ports

•

FC-PBGA–1295

37.5 mm

Two serial ATA (SATA) 2.0 controllers

Enhanced secure digital host controller (SD/MMC)

Enhanced serial peripheral interface (eSPI)

Two high-speed USB 2.0 controllers with integrated PHYs

RAID 5 and 6 storage accelerator with support for

end-to-end data protection information

• Data Path Acceleration Architecture (DPAA) incorporating

acceleration for the following functions:

– Frame Manager (FMan) for packet parsing,

classification, and distribution

– Queue Manager (QMan) for scheduling, packet

sequencing and congestion management

– Hardware Buffer Manager (BMan) for buffer allocation

and deallocation

– Encryption/Decryption

• 1295 FC-PBGA package

This figure shows the major functional units within the chip.

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

Table of Contents

Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .3

1.1 1295 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3

1.2 Pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .52

2.2 Power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .60

2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.5 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65

2.8 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .66

2.9 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .66

2.10 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

2.11 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

2.12 Ethernet: data path three-speed Ethernet (dTSEC),

management interface, IEEE Std 1588. . . . . . . . . . . . .77

2.13 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

2.14 Enhanced local bus interface (eLBC) . . . . . . . . . . . . . .87

2.15 Enhanced secure digital host controller (eSDHC) . . . .92

2.16 Multicore programmable interrupt controller (MPIC)

specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

2.18 I

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

2.19 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.20 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 101

Hardware design considerations . . . . . . . . . . . . . . . . . . . . . 129

3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . 136

3.3 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.4 Decoupling recommendations . . . . . . . . . . . . . . . . . . 139

3.5 SerDes block power supply decoupling recommendations

140

3.6 Connection recommendations. . . . . . . . . . . . . . . . . . 140

3.7 Recommended thermal model . . . . . . . . . . . . . . . . . 150

3.8 Thermal management information. . . . . . . . . . . . . . . 150

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 151

4.2 Mechanical dimensions of the FC-PBGA . . . . . . . . . 152

Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 153

6.2 Orderable part numbers addressed by this document 154

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

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