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UCC1570
UCC2570
UCC3570
Low Power Pulse Width Modulator
FEATURES
•
Low Power BiCMOS Process
•
85µA Start-up Current
•
1mA Run Current
•
1A Peak Gate Drive Output
•
Voltage Feed Forward
•
Programmable Duty Cycle Clamp
•
Optocoupler Interface
•
500kHz Operation
•
Soft Start
•
Fault Counting Shutdown
•
Fault Latch Off or Automatic Restart
DESCRIPTION
The UCC1570 family of pulse width modulators is intended for application
in isolated switching supplies using primary side control and a voltage
mode feedback loop. Made with a BiCMOS process, these devices feature
low startup current for efficient off-line starting with a bootstrapped low volt-
age supply. Operating current is also very low; yet these devices maintain
the ability to drive a power MOSFET gate at frequencies above 500kHz.
Voltage feedforward provides fast and accurate response to wide line volt-
age variation without the noise sensitivity of current mode control. Fast cur-
rent limiting is included with the ability to latch off after a programmable
number of repetitive faults has occurred. This allows the power supply to
ride through a temporary overload, while still shutting down in the event of
a permanent fault. Additional versatility is provided with a maximum duty
cycle clamp programmable within a 20% to 80% range and line voltage
sensing with a programmable window of allowable operation.
BLOCK DIAGRAM
FREQ
11
CLOCK
GENERATOR
CLK
RAMP
VALLEY
1V
VFWD
6
4.5V
10 I3
I3
S
RAMP
LATCH
R
10 I4
SLOPE
7
RAMP
10
1V
5V
GENERATOR
12
13
VREF
GND
15V
13/9V
ISET
9
I4
4V
HIGH
LINE
LOW
LINE
1V
FEEDBK
8
I4
SOFTST
14
PWM
S
R
D
PWM
LATCH
5
4
4V
RAMP
PEAK
3
VCC
OUT
PGND
CURLIM
2
0.2V
CURRENT
LIMIT
I4
S
D
CLK
COUNT
1
R
R
S
D
4V
SHUTDOWN
LATCH
SHUTDOWN
0.6V
04/99
UCC1570
UCC2570
UCC3570
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
(Limit Supply Current to 20mA) . . . . . . . Self Limiting at 15V
Supply Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20mA
Analog Inputs (CURLIM, VFWD, FEEBK) . . . . . . . . . . . . . . 6V
Programming Current I
SLOPE
, I
ISET
. . . . . . . . . . . . . . . . . –1mA
Output Current I
OUT
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±180mA
Pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±1.2A
CONNECTION DIAGRAMS
DIL-14 (TOP VIEW)
N or J Package
Note:
All voltages are with respect to GND. Currents are posi-
tive into the specified terminal. Consult Packaging Section of
Databook for thermal limitations and considerations of pack-
age.
PLCC-20 (TOP VIEW)
Q Package
SOIC-14 (TOP VIEW)
D Package
ORDERING INFORMATION
UCC1570J
UCC2570D
UCC2750N
UCC3570D
UCC3570N
UCC3570Q
Temperature Range
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
Package
Ceramic Dip
SOIC
Plastic Dip
SOIC
Plastic Dip
PLCC
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= 0 to 70°C for the
UCC3570, T
A
= –40 to 85°C for the UCC2570, T
A
=–55 to 125°C for the UCC1570, R
ISET
=100k, R
SLOPE
=121k, C
FREQ
=180pF,
C
RAMP
=150pF, VCC=11V and T
A
=T
J
.
PARAMETER
Reference
VREF
Line Regulation
Load Regulation
Short Circuit Current
VCC
Vth (On)
Vth (Off)
Hysteresis
VCC
I
VCC
Start
I
VCC Run
TEST CONDITIONS
VCC =10 to 13V, I
VREF
= 0 to 2mA
VCC = 10 to 13V
I
VREF
= 0 to 2mA
VREF = 0
12
8
3
13.5
Min
4.9
Typ
5
2
2
10
13
9
4
15
85
1
Max
5.1
10
10
50
Units
V
mV
mV
mA
V
V
V
V
µA
mA
I
VCC
= 10mA
VCC = 11V, VCC Comparator Off
VCC Comparator On
10
5
16
150
1.5
2
UCC1570
UCC2570
UCC3570
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= 0 to 70°C for the
UCC3570, T
A
= –40 to 85°C for the UCC2570, T
A
=–55 to 125°C for the UCC1570, R
ISET
=100k, R
SLOPE
=121k, C
FREQ
=180pF,
C
RAMP
=150pF, VCC=11V and T
A
=T
J
.
PARAMETER
Line Sense
Vth High Line Comparator
Vth Low Line Comparator
lib (VFWD)
Oscillator
Frequency
Ramp Generator
I
RAMP
/I
SLOPE
–I
RAMP
/I
ISET
Peak Ramp Voltage
Valley Ramp Voltage
ISET Voltage Level
Soft Start
Saturation
I
SOFTST
/I
ISET
Pulse Width Modulator
lib(FEEDBK)
FEEDBK
Current Limit
lib(CURLIM)
Vth Current Limit
Vth Shutdown
Fault Counter
Vth
Vsat
I
COUNT
/I
ISET
Output Driver
Vsat High
Vsat Low
Rise/Fall Time
I
OUT
= –100mA
I
OUT
= 100mA
C
OUT
= 1nF, (Note 1)
VCC = 11V, VCC Comparator Off
0.8
TEST CONDITIONS
Min
3.9
0.96
Typ
4
1
0
100
10
10
4
1
1
25
1
0
1
4
0
200
600
4
0
1
0.4
0.4
20
Max
4.1
1.04
±100
110
11
11
4.2
1.05
1.05
100
1.2
±100
1.1
4.2
±100
220
700
4.2
100
1.2
1
1
100
Units
V
V
nA
kHz
A/A
A/A
V
V
V
mV
A/A
nA
V
V
nA
mV
mV
V
mV
A/A
V
V
ns
90
9
9
3.8
0.95
0.95
Zero Duty Cycle
Maximum Duty Cycle, (Note 1)
0.9
3.8
180
500
3.8
0.8
Note 1:
This parameter guaranteed by design but not 100% tested in production.
PIN DESCRIPTIONS
VCC:
Chip supply voltage pin. Bypass to PGND with a
low ESL/ESR 0.1µF capacitor plus a capacitor for gate
charge storage. Lead lengths must be minimum.
PGND:
Ground pin for the output driver. Keep connec-
tions less than 2cm. Carefully maintain low impedance
path for high current return.
OUT:
Gate drive output pin. Connect to the gate of a
power MOSFET with a resistor greater than 2Ω. Keep
connection lengths under 2cm.
VFWD:
Voltage Feed Forward and Line Sense pin. Con-
nect to input DC line using a resistive divider.
SLOPE:
Program the charging current for RAMP with a
resistor from this pin to GND. This pin will follow VFWD.
FEEDBK:
Input to the pulse width modulator comparator.
Drive this pin with an optocoupler to GND and a resistor
to VREF. Modulation input range is from 1V to 4V.
ISET:
A resistor from this pin to GND programs RAMP
discharge current, FREQ current, SOFTST current, and
COUNT current.
3
UCC1570
UCC2570
UCC3570
PIN DESCRIPTIONS (cont.)
RAMP:
Ramp Pin. Connect a capacitor to GND. Rising
slope is programmed by current in SLOPE. This slope is
compared to FEEDBK for pulse width modulation. The
falling slope is programmed by the current in ISET and
used to limit maximum duty cycle.
FREQ:
Oscillator pin. Program the frequency with a ca-
pacitor to GND.
VREF:
Precision 5V reference, and bypass point for inter-
nal circuitry. Bypass this pin with a 1µF minimum capaci-
tor to GND.
GND:
Analog ground. Connect to a low impedance
ground plane containing all analog low current returns.
SOFTST:
Soft start pin. Program with a capacitor to
GND.
COUNT:
Program the time that fault events will be toler-
ated before shutdown occurs with a capacitor and resis-
tor to GND.
CURLIM:
Current Limit Sense pin. Terminates OUT gate
drive pulse for inputs over 0.2V. Enables fault counting
function (COUNT). For inputs over 0.6V, the shutdown
latch is activated.
APPLICATION INFORMATION
(Note: Refer to Typical Application for external compo-
nent names.) All the equations given below should be
considered as first order approximations with final values
determined empirically for a specific application.
Power Sequencing
VCC normally connects through a high impedance (R5)
to the rectified line, with an additional path(R6) to a low
voltage, bootstrap on the winding power transformer.
VFWD normally connects to a divider (R1 and R2) from
the rectified line. For circuit activation, all of the following
considerations are required:
1. VFWD between 1V and 4V
2. VCC has been under 9V (to reset the shutdown
latch)
3. VCC over 13V
At this time, the circuit will activate. I
VCC
will increase
from its start up value of 85µA to its run value of 1mA.
The capacitor on SOFTST is charged with a current de-
termined by:
–I
SOFTST
=
1
V
.
R
4
Output Inhibit
During normal operation, OUT is driven high at the start
of a clock period and back low when RAMP either
crosses FEEDBK or equals 4V. If, however, any of the fol-
lowing occur, OUT is immediately driven low for the re-
mainder of the clock period:
1. VFWD is outside the range of 1V to 4V
2. CURLIM is greater than 0.2V
3. FEEDBK or SOFTST is less than 1V
Normal output pulses will not resume until the beginning
of the next clock period in which none of the above con-
ditions exist.
Current Limiting
CURLIM is monitored by two internal comparators. The
current limit comparator threshold is 0.2V. If the current
limit comparator is triggered, OUT is immediately driven
low and held low for the remainder of the clock cycle,
providing pulse-by-pulse overcurrent control for exces-
sive loads. This comparator also causes C
F
to be
charged for the remainder of the clock cycle. The charg-
ing current is
–I
COUNT
=
1
V
.
R
4
When SOFTST rises above 1V, output pulses will begin
and I
VCC
will further rise to a level dictated by gate
charge requirements asI
VCC
≈
1mA + QTfs. With output
pulses, the low voltage bootstrap winding should now
power the controller. If VCC falls below 9V, the controller
will turn off and the start sequence will reset and retry.
VCC Clamp
An internal shunt regulator clamps VCC so that it will not
exceed 15V.
If repetitive cycles are terminated by the current limit
comparator causing COUNT to rise above 4V, the shut-
down latch is set. The COUNT integration delay feature
will be bypassed by the shutdown comparator which has
a 0.6V threshold. The shutdown comparator immediately
sets the shutdown latch. R
F
in parallel with C
F
resets the
COUNT integrator following transient faults. R
F
must be
(
4
•
R
4
)
.
greater than
(
1
−
D
MAX
)
4
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