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-1-
K4B2G1646F
datasheet
History
- First SPEC release
Draft Date
15th Jan. 2016
Rev. 1.0
DDR3 SDRAM
Revision History
Revision No.
1.0
Remark
-
Editor
J.Y.Lee
-2-
K4B2G1646F
datasheet
Rev. 1.0
DDR3 SDRAM
Table Of Contents
2Gb F-die DDR3 SDRAM Only x16
1. Ordering Information .....................................................................................................................................................5
6. Absolute Maximum Ratings ..........................................................................................................................................10
6.1 Absolute Maximum DC Ratings............................................................................................................................... 10
6.2 DRAM Component Operating Temperature Range ................................................................................................ 10
7. AC & DC Operating Conditions.....................................................................................................................................10
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 10
8. AC & DC Input Measurement Levels ............................................................................................................................11
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 11
8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)................................................... 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew rate definitions for Differential Input Signals ................................................................................................... 17
9. AC & DC Output Measurement Levels .........................................................................................................................18
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 18
9.2 Differential AC & DC Output Levels......................................................................................................................... 18
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 20
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 21
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 22
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 23
9.8 On-Die Termination (ODT) Levels and I-V Characteristics...................................................................................... 23
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 24
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 25
9.9.1. Test Load for ODT Timings .............................................................................................................................. 26
13.1.1. Definition for tCK(avg) .................................................................................................................................... 40
13.1.2. Definition for tCK(abs) .................................................................................................................................... 40
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 40
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 40
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 40
13.1.6. Definition for tERR(nper) ................................................................................................................................ 40
13.2 Refresh Parameters by Device Density................................................................................................................. 41
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 41
13.3.1. Speed Bin Table Notes .................................................................................................................................. 46
-3-
K4B2G1646F
datasheet
Rev. 1.0
DDR3 SDRAM
14. Timing Parameters by Speed Grade ..........................................................................................................................47
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 55
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 62
3. Backward Compatible to DDR3-1866(13-13-13), DDR3-1600(11-11-11), DDR3-1333(9-9-9)
4. Backward Compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9)
2. Key Features
[ Table 2 ] 2Gb DDR3 F-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
DDR3-1866
13-13-13
1.071
13
13.91
13.91
34
47.91
DDR3-2133
14-14-14
0.938
14
13.09
13.09
33
46.09
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
DDQ
= 1.5V ± 0.075V
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin,
933MHz f
CK
for 1866Mb/sec/pin, 1066MHz f
CK
for 2133Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13,14
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600), 9(DDR3-1866) and
10(DDR3-2133)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85C, 3.9us at
85C < T
CASE
< 95
C
•
•
•
•
Asynchronous Reset
Package : 96 balls FBGA - x16
All of Lead-Free products are compliant for RoHS
All of products are Halogen-free
The 2Gb DDR3 SDRAM F-die is organized as a 16Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 2133Mb/sec/pin (DDR3-2133) for general applica-
tions.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V
DDQ
.
The 2Gb DDR3 F-die device is available in 96balls FBGA(x16).
NOTE
: 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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