EEWORLDEEWORLDEEWORLD

Part Number

Search

A3P125-FGG100ES

Description
FPGA, 768 CLBS, 30000 GATES, 350 MHz, PQFP100
Categorysemiconductor    Programmable logic devices   
File Size10MB,220 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

A3P125-FGG100ES Overview

FPGA, 768 CLBS, 30000 GATES, 350 MHz, PQFP100

A3P125-FGG100ES Parametric

Parameter NameAttribute value
Number of terminals100
Minimum operating temperature-40 Cel
Maximum operating temperature85 Cel
Processing package description14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, VQFP-100
each_compliYes
EU RoHS regulationsYes
stateActive
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max350 MHz
jesd_30_codeS-PQFP-G100
jesd_609_codee3
moisture_sensitivity_level3
Number of configurable logic modules768
Number of equivalent gate circuits30000
organize768 CLBS, 30000 GATES
Packaging MaterialsPLASTIC/EPOXY
ckage_codeTFQFP
packaging shapeSQUARE
Package SizeFLATPACK, THIN PROFILE, FINE PITCH
eak_reflow_temperature__cel_260
qualification_statusCOMMERCIAL
seated_height_max1.2 mm
Rated supply voltage1.5 V
Minimum supply voltage1.42 V
Maximum supply voltage1.58 V
surface mountYES
CraftsmanshipCMOS
Temperature levelINDUSTRIAL
terminal coatingMATTE TIN
Terminal formGULL WING
Terminal spacing0.5000 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_40
length14 mm
width14 mm
Revision 13
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM
®
-enabled ProASIC
®
3 devices)
via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
Embedded Memory
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in ProASIC3 FPGAs
ProASIC3 Devices
Cortex-M1 Devices
2
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP
3
Integrated PLL in CCCs
VersaNet Globals
4
I/O Banks
Maximum User I/Os
Package Pins
QFN
CS
VQFP
TQFP
PQFP
FBGA
A3P015
1
15,000
128
384
1
6
2
49
QN68
A3P030
30,000
256
768
1
6
2
81
QN48, QN68,
QN132
VQ100
A3P060
60,000
512
1,536
18
4
1
Yes
1
18
2
96
QN132
CS121
VQ100
TQ144
FG144
A3P125
125,000
1,024
3,072
36
8
1
Yes
1
18
2
133
QN132
VQ100
TQ144
PQ208
FG144
A3P250
M1A3P250
250,000
2,048
6,144
36
8
1
Yes
1
18
4
157
QN132
5
VQ100
PQ208
PQ208
FG144/256
5
FG144/256/
484
PQ208
FG144/256/
484
A3P400
M1A3P400
400,000
9,216
54
12
1
Yes
1
18
4
194
A3P600
M1A3P600
600,000
13,824
108
24
1
Yes
1
18
4
235
• M1 ProASIC3 Devices—ARM
®
Cortex™-M1 Soft Processor
Available with or without Debug
A3P1000
M1A3P1000
1,000,000
24,576
144
32
1
Yes
1
18
4
300
PQ208
FG144/256/
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the
Cortex-M1
product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the
ProASIC3E Flash Family FPGAs
datasheet.
† A3P015 and A3P030 devices do not support this feature.
January 2013
© 2013 Microsemi Corporation
‡ Supported only by A3P015 and A3P030 devices.
I
Simple fast short circuit protection circuit.jpg
[i=s] This post was last edited by paulhyde on 2014-9-15 09:38 [/i] Simple fast short circuit protection circuit...
zhshmzd123654 Electronics Design Contest
Ask, microcontroller interrupt
How do I set up a timer interrupt? How do I set up a random IO port as an interrupt pin?...
不过机子 51mcu
How is I2>>IB derived in the DC path of the voltage divider bias circuit?
In the DC path of the voltage divider bias circuit, the book says that the current I2 on the bias resistor R2 is much larger than the base current IB, that is, I2>>IB. How is this derived?...
Erespreciosa Embedded System
Two problems encountered when running MIG layout and routing simulation: unable to call the signal line under the module and not recognizing the DDR behavior model
The background is to control the DDR SDRAM controller generated by MIG. The test environment is as follows: the top layer is TESTBENCH written by me, and there are two models under the top layer, one ...
zhj1985 FPGA/CPLD
Problems encountered in debugging Pingtouge's scenario-based Bluetooth Mesh
[i=s]This post was last edited by littleshrimp on 2021-10-30 14:14[/i]Today, I am preparing to connect the module to the network according to the Bluetooth MESH Gateway Development Board Quick Start G...
littleshrimp Domestic Chip Exchange
A question about the amplification factor of triode
I would like to ask a question about the amplification factor of a transistor . In practical applications, the voltage amplification factor β of a transistor is uncertain, so how can we know the actua...
beandy Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2722  1846  870  2116  2725  55  38  18  43  51 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号