A3PN0302VQG100YPP datasheet, PDF

Datasheet> All Categories > A3PN0302VQG100YPP

Preview

A3PN0302VQG100YPP: DescriptionProASIC3 nano Flash FPGAs; File Size6MB，114 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet View All

A3PN0302VQG100YPP Overview

ProASIC3 nano Flash FPGAs

Preview

Download Datasheet

View All

Revision 11

ProASIC3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

†

• FlashLock

Designed to Secure FPGA Contents

Clock Conditioning Circuit (CCC) and PLL

†

Low Power

•

Low Power

nano Products

1.5 V Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

ProASIC

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18 organization)

†

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Enhanced Commercial Temperature Range

• –20°C to +70°C

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices

ProASIC3 nano-Z Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

A3PN010

10,000

260

–

A3PN015

A3PN020

15,000

128

384

–

QN68

20,000

172

520

–

QN68

30,000

256

768

–

QN48, QN68

VQ100

A3PN060

60,000

512

1,536

Yes

A3PN125

125,000

1,024

3,072

Yes

A3PN250

A3N250Z

250,000

2,048

6,144

Yes

A3PN030Z

1,2

A3PN060Z

A3PN125Z

FlashROM Kbits

Secure (AES) ISP

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

QFN

VQFP

–

QN48

Integrated PLL in CCCs

VQ100

Notes:

1. Not recommended for new designs.

2. A3PN030Z and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the

ProASIC3

and

ProASIC3E

datasheets.

† A3PN030 and smaller devices do not support this feature.

January 2013

ProASIC3 nano Flash FPGAs

Table of Contents

ProASIC3 nano Device Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3 nano DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-3

3-4

Package Pin Assignments

48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

R ev i si o n 1 1

Recommended Resources

Practical AM-4 module circuit schematic designed using TGS4160 sensor

Inductive proximity switch circuit

Anti-theft alarm circuit for valuable home appliances

External control circuit of general frequency converter

Astable circuits prone to oscillation

(Classic) Motorola L7 mobile phone schematic 1/7

Subtraction counter 2 in ds18b20: There is a sentence in the working principle of ds18b20 temperature sensor: "The cycle continues until the subtraction counter 2 counts to 0, and the accumulation of the temperature register value sto...; chenyaoxin Analog electronics

There are several layers of structure from application software to underlying hardware in Windows system: How many layers of structure are there from application software to the underlying hardware in Windows system? What are the conditions of each aspect?...; nuanshuiping Embedded System

ADS1100 16-bit analog-to-digital converter based on I2C bus: [table=98%] [tr][td][backcolor=white][color=#000000][font=Courier]It has the advantages of high resolution, simple interface, proportional amplification, low power consumption and small size. ADS1100 ...; 莫妮卡 Analogue and Mixed Signal

Compile QT5 application with qt creator: Compiler: ARM-poky-linux-gnueabi-gcc-file version: L4115-fsl-image-qt5-myimx6a9.tar.bz2 ... [color=#333333][font=微软雅黑]Install tutorial compilation tool:[/font][/color] [color=#333333][font=微软雅黑]chmod ...; 明远智睿Lan Industrial Control Electronics

[Feiling S5PV210 development board] [Processor] Introduction: S5PV210 is a 32-bit RISC, low power, high performance cortex-a8 processor, which belongs to the armv7 architecture. The Feiling development board model is OK210. 120404 The picture above shows the ove...; forlinx2013 ARM Technology

Which version of ad software is better?: I have been using protel99se. I want to learn AD. I don't know which version is more stable and better? Thank you :)...; 余与鱼 PCB Design

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components