AGL600V2-UC484PP datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> AGL600V2-UC484PP

AGL600V2-UC484PP: DescriptionFPGA, 24576 CLBS, 1000000 GATES, 108 MHz, PBGA484; Categorysemiconductor Programmable logic devices; File Size12MB，250 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

AGL600V2-UC484PP Overview

FPGA, 24576 CLBS, 1000000 GATES, 108 MHz, PBGA484

AGL600V2-UC484PP Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	484
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN LEAD SILVER
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
organize	24576 CLBS, 1000000 GATES
Maximum FCLK clock frequency	108 MHz
Number of configurable logic modules	24576
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	1.00E6

Preview

Download Datasheet

View All

Revision 23

IGLOO Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• 15K to 1 Million System Gates

• Up to 144 Kbits of True Dual-Port SRAM

• Up to 300 User I/Os

•

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X

†

and LVCMOS 2.5 V / 5.0 V Input

†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

‡

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit

†

RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)

†

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

AGL250

M1AGL250

250,000

2,048

6,144

Yes

143

CS81, CS196

QN132

5,6

VQ100

FG144

FG144, FG256, FG144, FG256, FG144, FG256,

FG484

High Capacity

Reprogrammable Flash Technology

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

High-Performance Routing Hierarchy

Advanced I/O

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM

-enabled IGLOO

devices) via

JTAG (IEEE 1532–compliant)

†

• FlashLock

Designed to Secure FPGA Contents

• Segmented, Hierarchical Routing and Clock Structure

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Embedded Memory

ARM Processor Support in IGLOO FPGAs

IGLOO Devices

AGL015

ARM-Enabled IGLOO Devices

System Gates

15,000

Typical Equivalent Macrocells

128

VersaTiles (D-flip-flops)

384

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

–

4,608-Bit Blocks

–

FlashROM Kbits (1,024 bits)

AES-Protected ISP

–

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

UC/CS

QFN

VQFP

FBGA

QN68

AGL030

30,000

256

768

–

AGL060 AGL125

60,000

512

1,536

Yes

125,000

1,024

3,072

Yes

133

CS196

QN132

VQ100

FG144

AGL400

400,000

–

9,216

Yes

194

CS196

AGL600

M1AGL600

600,000

–

13,824

108

Yes

235

CS281

AGL1000

M1AGL1000

1,000,000

–

24,576

144

Yes

300

CS281

UC81

CS121

CS81

QN48, QN68, QN132

QN132

VQ100

FG144

Notes:

AGL015 is not recommended for new designs

AES is not available for ARM-enabled IGLOO devices.

AGL060 in CS121 does not support the PLL.

Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

The M1AGL250 device does not support this package.

Device/package support TBD.

The

IGLOOe

datasheet and

IGLOOe FPGA Fabric User’s Guide

provide information on higher densities and additional features.

† AGL015 and AGL030 devices do not support this feature.

December 2012

‡ Supported only by AGL015 and AGL030 devices.

IGLOO Low Power Flash FPGAs

Table of Contents

IGLOO Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

IGLOO DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-4

3-5

Package Pin Assignments

UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37

FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

R ev i si o n 2 3

Recommended Resources

Image and text decoder circuit using SDA5273-75 chip

DC motor drive integrated circuit

Gated night light circuit

Dual tone alarm circuit

Simple ultra-high voltage generator

10~65V regulated power supply circuit

Design of wireless transmission system based on nRF2401: [font=宋体][size=10.5pt]Use nrf2401 chip and 51 series single chip microcomputer to design a wireless data transmission system. Please ask the expert for the circuit diagram urgently! ! ! [/size][/font]...; ning1020 MCU

Inside Apple's A7 chip: Exploring transistors: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:59[/i] [align=left][color=#000][font=Simsun][size=3]Apple's A7 processor is not only very advanced in technology, but also a representa...; wstt Mobile and portable

Realization of FIR digital filter using DSP: FIR filters have the advantages of arbitrary amplitude characteristics and strict and accurate linear phase characteristics. Therefore, they are very attractive in modern electronic systems that requi...; 小赛跑跑 DSP and ARM Processors

bq2084 + bq29312A layout guide: Could you please provide me with the bq2084 + bq29312A layout guide? Thanks!...; CTSGARY PCB Design

Who has developed a complete solution for WIFI cameras?: [color=rgb(51, 51, 51)][font=微软雅黑,]WIFI camera complete solution development[/font][/color] [color=rgb(51, 51, 51)][font=微软雅黑,]1. Realize WIFI connection through WIFI router[/font][/color] [color=rgb(...; 1977650578 Industrial Control Electronics

EEWORLD Chip Coin Bidding——Three Books: [font=微软雅黑][size=3]The three books participating in the core currency bidding this time are: [/size][/font] [b][font=微软雅黑][size=3]A "The Art of Linux Kernel Design" [/size][/font] [font=微软雅黑][size=3]B...; eric_wang Talking

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components