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AGLN250V5-VQG100Y

Description
FPGA, 520 CLBS, 20000 GATES, PBGA81
CategoryProgrammable logic devices    Programmable logic   
File Size7MB,148 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
Download Datasheet Parametric View All

AGLN250V5-VQG100Y Overview

FPGA, 520 CLBS, 20000 GATES, PBGA81

AGLN250V5-VQG100Y Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrosemi
package instructionTFQFP, TQFP100,.63SQ
Reach Compliance Codecompli
maximum clock frequency250 MHz
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
Humidity sensitivity level3
Configurable number of logic blocks6144
Equivalent number of gates250000
Number of entries68
Number of logical units6144
Output times68
Number of terminals100
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
organize6144 CLBS, 250000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeTFQFP
Encapsulate equivalent codeTQFP100,.63SQ
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Revision 19
DS0110
IGLOO nano Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
nanoPower Consumption—Industry’s Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
• As Small as 3x3 mm in Size
High-Performance Routing Hierarchy
Advanced I/Os
• Segmented, Hierarchical Routing and Clock Structure
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO
®
Family
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except × 18 organization)
• Tj = -20°C to +85°C
Small Footprint Packages
Wide Range of Features
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
• 10,000 to 250,000 System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
Embedded Memory
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
Designed to Secure FPGA Contents
• 1.2 V Programming
Enhanced Commercial Temperature Range
AGLN060
AGLN030Z
1
IGLOO nano Devices
IGLOO nano-Z Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM Kbits (1,024 bits)
2
4,608-Bit Blocks
Secure (AES)
2
1
AGLN010 AGLN015
1
AGLN020
10,000
86
260
2
1
2,3
AGLN125
1
AGLN250
1
AGLN060Z
60,000
512
1,536
10
18
4
1
Yes
1
18
2
71
71
AGLN125Z
125,000
1,024
3,072
16
36
8
1
Yes
1
18
2
71
71
AGLN250Z
1
250,000
2,048
6,144
24
36
8
1
Yes
1
18
4
68
68
15,000
128
384
4
1
4
3
49
20,000
172
520
4
1
4
3
52
52
30,000
256
768
5
1
6
2
77
83
FlashROM Kbits (1,024 bits)
ISP
2
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
4
2
34
34
† AGLN030 and smaller devices do not support this feature.
October 2015
© 2015 Microsemi Corporation
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