Features
•
Single 2.3V - 3.6V or 2.7V - 3.6V Supply
•
Serial Peripheral Interface (SPI) Compatible
•
•
– Supports SPI Modes 0 and 3
70 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– One 16-Kbyte Top Sector
– Two 8-Kbyte Sectors
– One 32-Kbyte Sector
– Seven 64-Kbyte Sectors
Hardware Controlled Locking of Protected Sectors via WP pin
Flexible Programming Options
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
Fast Program and Erase Times
– 1.2 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5 mA Active Read Current (Typical)
– 15 µA Deep Power-down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil Wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
•
•
•
4-megabit
2.3-volt or
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25DF041A
•
•
•
•
•
•
•
•
1. Description
The AT25DF041A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF041A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
3668D–DFLASH–9/08
The physical sectoring and the erase block sizes of the AT25DF041A have been optimized to
meet the needs of today’s code and data storage applications. By optimizing the size of the
physical sectors and erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their
own protected sectors, the wasted and unused memory space that occurs with large sectored
and large block erase Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional code routines and data storage segments to be added while
still maintaining the same overall device density.
The AT25DF041A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT25DF041A incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
Specifically designed for use in 2.5-volt or 3-volt systems, the AT25DF041A supports read, pro-
gram, and erase operations with a supply voltage range of 2.3V to 3.6V or 2.7V to 3.6V. No
separate voltage is required for programming and erasing.
2
AT25DF041A
3668D–DFLASH–9/08
AT25DF041A
2. Pin Descriptions and Pinouts
Table 2-1.
Symbol
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT:
The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
SERIAL OUTPUT:
The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
WRITE PROTECT:
The WP pin controls the hardware locking feature of the device. Please refer to
section
“Protection Commands and Features” on page 15
for more details on protection features
and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
HOLD:
The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section
“Hold”
on page 30
for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to V
CC
whenever
possible.
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the
system ground.
Asserted
State
Type
CS
Low
Input
SCK
Input
SI
Input
SO
Output
WP
Low
Input
HOLD
Low
Input
V
CC
GND
Power
Power
Figure 2-1.
CS
SO
WP
GND
8-SOIC Top View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-2.
CS
SO
WP
GND
8-UDFN Top View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
3
3668D–DFLASH–9/08
3. Block Diagram
CS
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SCK
SI
SO
SRAM
DATA BUFFER
INTERFACE
CONTROL
AND
LOGIC
ADDRESS LATCH
Y-DECODER
Y-GATING
WP
X-DECODER
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions.
Figure 4-1 on page 5
illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
4
AT25DF041A
3668D–DFLASH–9/08
AT25DF041A
Figure 4-1.
Memory Architecture Diagram
Block Erase Detail
Internal
Sectoring
for
Sector
Protection
Function
64KB
32KB
Block Erase
Block Erase
(D8h Command) (52h Command)
4KB
Block Erase
(20h Command)
Block Address
Range
Page Program Detail
1-256 Byte
Page Program
(02h Command)
Page Address
Range
16KB
(Sector 10)
8KB
(Sector 9)
8KB
(Sector 8)
32KB
64KB
32KB
(Sector 7)
32KB
32KB
32KB
32KB
64KB
(Sector 0)
64KB
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00F F F F h –
00E F F F h –
00DF F F h –
00CF F F h –
00BF F F h –
00AF F F h –
009F F F h –
008F F F h –
007F F F h –
006F F F h –
005F F F h –
004F F F h –
003F F F h –
002F F F h –
001F F F h –
000F F F h –
00F 000h
00E 000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
•••
64KB
(Sector 6)
64KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
•••
07F F F F h –
07E F F F h –
07DF F F h –
07CF F F h –
07BF F F h –
07AF F F h –
079F F F h –
078F F F h –
077F F F h –
076F F F h –
075F F F h –
074F F F h –
073F F F h –
072F F F h –
071F F F h –
070F F F h –
06F F F F h –
06E F F F h –
06DF F F h –
06CF F F h –
06BF F F h –
06AF F F h –
069F F F h –
068F F F h –
067F F F h –
066F F F h –
065F F F h –
064F F F h –
063F F F h –
062F F F h –
061F F F h –
060F F F h –
07F 000h
07E 000h
07D000h
07C000h
07B000h
07A000h
079000h
078000h
077000h
076000h
075000h
074000h
073000h
072000h
071000h
070000h
06F 000h
06E 000h
06D000h
06C000h
06B000h
06A000h
069000h
068000h
067000h
066000h
065000h
064000h
063000h
062000h
061000h
060000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
07F F F F h –
07F E F F h –
07F DF F h –
07F CF F h –
07F BF F h –
07F AF F h –
07F 9F F h –
07F 8F F h –
07F 7F F h –
07F 6F F h –
07F 5F F h –
07F 4F F h –
07F 3F F h –
07F 2F F h –
07F 1F F h –
07F 0F F h –
07E F F F h –
07E E F F h –
07E DF F h –
07E CF F h –
07E BF F h –
07E AF F h –
07E 9F F h –
07E 8F F h –
07F F 00h
07F E 00h
07F D00h
07F C00h
07F B00h
07F A00h
07F 900h
07F 800h
07F 700h
07F 600h
07F 500h
07F 400h
07F 300h
07F 200h
07F 100h
07F 000h
07E F 00h
07E E 00h
07E D00h
07E C00h
07E B00h
07E A00h
07E 900h
07E 800h
0017F F h
0016F F h
0015F F h
0014F F h
0013F F h
0012F F h
0011F F h
0010F F h
000F F F h
000E F F h
000DF F h
000CF F h
000BF F h
000AF F h
0009F F h
0008F F h
0007F F h
0006F F h
0005F F h
0004F F h
0003F F h
0002F F h
0001F F h
0000F F h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
001700h
001600h
001500h
001400h
001300h
001200h
001100h
001000h
000F 00h
000E 00h
000D00h
000C00h
000B00h
000A00h
000900h
000800h
000700h
000600h
000500h
000400h
000300h
000200h
000100h
000000h
•••
•••
•••
5
3668D–DFLASH–9/08
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