MP7529B
5 V CMOS
Dual Buffered Multiplying 8-Bit
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
Very Low Total Harmonic Distortion
Low Glitch Energy
Fast Settling Time
Four Quadrant Multiplication
On-Chip Latches for Both DACs
4.5 V to 5.5 V Operation
Low Power Consumption
TTL/5V CMOS Compatible
Latch-Up Free
15 V Operation: MP7529A
BENEFITS
•
Quiet Operation in Audio Applications
•
Easy Interface to Microprocessors
GENERAL DESCRIPTION
The MP7529B is a dual 8-bit Digital-to-Analog Converter
featuring excellent DAC to DAC matching, tracking and
specifically optimized for applications requiring low total
harmonic distortion. The MP7529B is manufactured using
advanced thin film resistors on a double metal CMOS process.
The MP7529B incorporates a unique bit decoding technique
yielding lower glitch energy, higher speed and excellent
accuracy over temperature and time.
Data is transferred to either of the two D/A Converter latches
via a common 8-bit TTL/5 V CMOS compatible input port. The
control input DAC A/DAC B determines which D/A is to be
loaded.
The device operates from a 4.5 V to 5.5 V power supply, and
is TTL-compatible over this range. Power dissipation is only 10
mW. Both DACs offer excellent four quadrant multiplication
characteristics, and include separate reference inputs and
feedback resistors. An improved latch-up resistant design
eliminates the need for external protective Schottky diodes in
most applications.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
V
DD
V
REFA
DB7-DB0
DAC A/DAC B
CS
WR
R
FBB
D
Q
LATCH B
E
DAC B
I
OUTB
AGND
OUT
R
FBA
DB7-DB0
DAC A/DAC B
D
Q
LATCH A
E
DAC A
I
OUTA
CS
WR
DGND
V
REFB
Rev. 2.00
1
MP7529B
ORDERING INFORMATION
Package
Type
Plastic Dip
Plastic Dip
SOIC
SOIC
PLCC
PLCC
Temperature
Range
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
Part No.
MP7529BJN
MP7529BKN
MP7529BJS
MP7529BKS
MP7529BJP
MP7529BKP
INL
(LSB)
+1
+1/2
+1
+1/2
+1
+1/2
DNL
(LSB)
+1
+1
+1
+1
+1
+1
Gain Error
(LSB)
+5
+3
+5
+3
+5
+3
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
I
OUTB
I
OUTA
AGND
R
FBA
R
FBB
3
2
1
20
19
AGND
I
OUTA
R
FBA
V
REFA
DGND
DAC A/DAC B
(MSB) DB7
DB6
DB5
DB4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
OUTB
R
FBB
V
REFB
V
DD
WR
CS
DB0 (LSB)
DB1
DB2
DB3
1
2
3
4
5
6
7
8
9
10
20
19
18
V
REFA
DGND
DAC A/DAC B
(MSB) DB7
DB6
4
5
6
7
8
18
17
16
15
14
V
REFB
V
DD
WR
CS
DB0
(LSB)
See
Pin Out
at Left
17
16
15
14
13
12
11
9
10
11
12
13
DB3
DB1
DB5
DB4
DB2
20 Pin PDIP (0.300”)
N20
20 Pin SOIC (Jedec, 0.300”)
S20
20 Pin PLCC
P20
PIN OUT DEFINITIONS
PIN NO.
1
2
3
4
5
6
7
8
9
10
NAME
AGND
I
OUTA
R
FBA
V
REFA
DGND
DACA/
DACB
DB7
DB6
DB5
DB4
DESCRIPTION
Analog Ground
Current Output of DAC A
Internal Feedback Resistor of DAC A
Reference Input Voltage of DAC A
Digital Ground
DAC selection control
Data Input Bit 7 (MSB)
Data Input Bit 6
Data Input Bit 5
Data Input Bit 4
PIN NO.
11
12
13
14
15
16
17
18
19
20
NAME
DB3
DB2
DB1
DB0
CS
WR
V
DD
V
REFB
R
FBB
I
OUTB
DESCRIPTION
Data Input Bit 3
Data Input Bit 2
Data Input Bit 1
Data Input Bit 0 (LSB)
Chip Select (Active Low)
Write Enable (Active Low)
Power Supply
Reference Input Voltage of DAC B
Internal Feedback Resistor of DAC B
Current Output of DAC B
Rev. 2.00
2
MP7529B
ELECTRICAL CHARACTERISTICS
(V
DD
= 4.5 V to 5.5 V, Nominal V
DD
= 5 V, V
REF
= 10 V unless otherwise noted)
Parameter
STATIC PERFORMANCE
1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
J
K
Differential Non-Linearity
J
K
Gain Error
J
K
Gain Temperature Coefficient
2
Power Supply Rejection Ratio
Output Leakage Current
DYNAMIC PERFORMANCE
2
Harmonic Distortion
Digital Crosstalk
AC Feedthrough
V
REFA
to I
OUTA
V
REFB
to I
OUTB
Channel-to-Channel Isolation
V
REFA
to I
OUTB
V
REFB
to I
OUTA
Glitch Energy
Current Settling Time
Propagation Delay
THD
Q
F
T
F
TA
F
TB
CCI
C
CIBA
C
CIAB
Egl
t
S
t
PD
–95
30
–70
–70
–77
–77
10
200
100
–65
–65
dB
nVs
dB
dB
dB
dB
dB
dB
nVs
ns
ns
V
IN
= 6V
RMS
@ 1 KHz
N
INL
+1
+1/2
DNL
+1
+1
GE
+4
+2
TC
GE
PSRR
I
LKG
+15
+100
+50
+5
+3
+15
+200
+200
ppm/°C
ppm/%
nA
∆Gain/∆Temperature
|∆Gain/∆V
DD
|, ∆V
DD
= + 5%
V
DD
= 4.75 V, +5%, & 5.25 V +5%
+1
+1
LSB
+1
+1/2
LSB
All grades monotonic over full
temperature range.
Using Internal R
FB
8
8
Bits
LSB
End Point Linearity Spec.
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
250
150
All zeros to all ones Input Change.
To 1/2 LSB,R
L
=100Ω, C
EXT
=13pF
From 50% of digital input to 90%
of final analog output current
R
L
=100Ω, C
EXT
=13pF
REFERENCE INPUT
Input Resistance
Input Resistance Matching
DIGITAL INPUTS
3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance
2
Data
Control
V
IH
V
IL
I
LKG
C
IN
C
IN
2.4
0.8
+1
10
15
2.4
0.8
+10
10
15
V
V
R
IN
8
15
+1
8
15
+1
kΩ
%
µ
A
pF
pF
Rev. 2.00
3
MP7529B
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
ANALOG OUTPUTS
2
Output Capacitance
C
OUTA/B
C
OUTA/B
POWER SUPPLY
Supply Current
TIMING SPECIFICATIONS
4
Chip Select to Write Set-Up Time
Chip Select to Write Hold Time
DAC Select to Write Set-Up Time
DAC Select to Write Hold Time
Data Valid to Write Set-Up Time
Data Valid to Write Hold Time
Write Pulse Width
5
t
CS
t
CH
t
AS
t
AH
t
DS
t
DH
t
WR
60
15
60
15
60
0
60
80
20
80
20
80
0
80
ns
ns
ns
ns
ns
ns
ns
I
DD
1
2
1
2
mA
mA
All digital inputs = 0 V or 5 V
All digital inputs = V
IL
or V
IH
120
50
120
50
pF
pF
DAC inputs all 1’s
DAC inputs all 0’s
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
NOTES:
1
Full Scale Range (FSR) is 10V for unipolar mode.
2
Guaranteed but not production tested.
3
Digital input levels should not go below GND or exceed the positive supply voltage, otherwise damage may occur.
4
See timing diagram.
5
t
WR
= 40ns minimum if t
DH
> 15ns (@T = 25°C)
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2, 3
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Digital Input Voltage to GND . . . . GND –0.5 to V
DD
+0.5 V
I
OUTA
, I
OUTB
to GND . . . . . . . . . . . GND –0.5 to V
DD
+0.5 V
V
REFA
, V
REFB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
V
RFBA
, V
RFBB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
Storage Temperature . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300
°
C
Package Power Dissipation Rating to 75
°
C
PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 900mW
Derates above 75
°
C . . . . . . . . . . . . . . . . . . . . . 12mW/
°
C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
All inputs have protection diodes
which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
µ
s.
3
GND refers to AGND and DGND.
Rev. 2.00
4
MP7529B
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can ac-
cept data from the input port. Inputs CS and WR control the op-
erating mode of the selected DAC (Table
1.).
When CS and WR
t
CS
CS
t
AS
DAC A/
DAC B
VALID
t
WR
WR
t
DS
DB7-DB0
VALID
t
DH
t
AH
t
CH
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The se-
lected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches (Hold mode).
DAC A/
DAC B
L
H
X
X
L = Low State
CS
WR
DAC A
WRITE
HOLD
HOLD
HOLD
X = Don’t Care
DAC B
HOLD
WRITE
HOLD
HOLD
L
L
L
L
H
X
X
H
H = High State
NOTE:
1. Timing measured from (V
IH
+ V
IL
) /2
Figure 1. Write Cycle Timing Diagram
Table 1. DAC’s Mode Selection
MICROPROCESSOR INTERFACE
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
A0-A15
A**
V
MA
CPU
6800
ADDRESS
DECODE
LOGIC
Address Bus
DAC A/DAC B
CS
A+1***
DAC A
A8-A15
A**
CPU
8085
WR
ALE
AD0–AD7
ADDRESS
DECODE
LOGIC
Address Bus
DAC A/DAC B
CS
A+1***
LATCH
8212
DAC A
φ
2
WR MP7529B*
DAC B
DB0
DB7
Data Bus
WR
DB0
DB7
MP7529B*
DAC B
D0–D7
ADDR/Data Bus
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 7529B DAC B Address
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 752B9 DAC B Address
Figure 2. MP7529B Dual DAC to 6800
CPU Interface
Figure 3. MP7529B Dual DAC to 8085
CPU Interface
Rev. 2.00
5
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