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Datasheet> All Categories > Passive components> capacitor> VJ2225A682GXBAB5H
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VJ2225A682GXBAB5H

Description
CAPACITOR, CERAMIC, MULTILAYER, 100 V, C0G, 0.0068 uF, SURFACE MOUNT, 2225, CHIP, ROHS COMPLIANT
CategoryPassive components    capacitor   
File Size153KB，8 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance  
Download Datasheet Parametric View All

VJ2225A682GXBAB5H Overview

CAPACITOR, CERAMIC, MULTILAYER, 100 V, C0G, 0.0068 uF, SURFACE MOUNT, 2225, CHIP, ROHS COMPLIANT

VJ2225A682GXBAB5H Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVishay
package instruction, 2225
Reach Compliance Codecompli
ECCN codeEAR99
capacitance0.0068 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee3
Manufacturer's serial numberVJ
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance2%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingBULK
positive tolerance2%
Rated (DC) voltage (URdc)100 V
size code2225
surface mountYES
Temperature characteristic codeC0G
Temperature Coefficient-/+30ppm/Cel ppm/°C
Terminal surfaceMatte Tin (Sn) - with Nickel (Ni) barrie
Terminal shapeWRAPAROUND

VJ2225A682GXBAB5H Preview

VJ OMD - C0G (NP0)
Vishay Vitramon
Surface Mount Multilayer Ceramic Chip Capacitor Solutions
for Boardflex Sensitive Applications
FEATURES
•
Surface mountable. Precious metal technology,
wet build process
•
OMD-Cap (Open Mode Design) reduce the risk
of shorts or low IR because of board flex cracks
•
High frequency filtering for switching power
supplies
•
Available with 100 % voltage condition,
process code “5H” is available for 630 V and lower.
Contact mlcc.specials@vishay.com for higher voltages
•
Available with polymer termination for increase resistance
to board flex cracking
•
Protective surface coating high voltage capacitors
maybe required to prevent surface arcing.
RoHS
COMPLIANT
APPLICATIONS
•
•
•
•
Input filter capacitors
Output filter capacitors
Snubber capacitors reduce MOSFET voltage spikes
Lighting Ballasts
ELECTRICAL SPECIFICATIONS
Note:
Electrical characteristics at + 25 °C unless otherwise stated
Operating Temperature:
- 55 °C to + 125 °C
Capacitance Range:
10 pF to 47 000
pF
Voltage Rating:
50 Vdc to 3000 Vdc
Temperature Coefficient of Capacitance (TCC):
C0G: 0 ± 30 ppm/°C from - 55 °C to + 125 °C
Aging Rate:
0 % maximum per decade
Dissipation Factor:
0.1 % max. at 1.0 V
rms
and 1 MHz for values
≤
1000 pF
0.1 % max. at 1.0 V
rms
and 1 kHz for values > 1000 pF
Insulation Resistance (IR):
At + 25 °C and rated voltage 100 000 MΩ minimum or
1000
ΩF,
whichever is less
At + 125 °C and rated voltage 10 000 MΩ minimum or
100
ΩF,
whichever is less
Dielectric Withstanding Voltage (DWV):
This is the maximum voltage the capacitors are tested for
a 1 to 5 second period and the charge/discharge current
does not exceed 50 mA
≤
200 Vdc: DWV at 250 % of rated voltage
500 Vdc: DWV at 200 % of rated voltage
630 Vdc: DWV at 150 % of rated voltage
1000 Vdc: DWV at 150 % of rated voltage
1500 Vdc: DWV at 120 % of rated voltage
2000 Vdc: DWV at 120 % of rated voltage
3000 Vdc: DWV at 120 % of rated voltage
Document Number 45047
Revision: 16-Aug-07
For technical questions, contact: mlcc.specials@vishay.com
www.vishay.com
5
VJ OMD - C0G (NP0)
Vishay Vitramon
Surface Mount Multilayer Ceramic Chip Capacitor Solutions
for Boardflex Sensitive Applications
DIMENSIONS
in inches [millimeters]
PART
ORDERING
NUMBER
VJ1206
LENGTH
0.126 ± 0.008
[3.20 ± 0.20]
0.126 ± 0.008
[3.20 ± 0.20]
0.180 ± 0.010
[4.57 ± 0.25]
0.177 ± 0.010
[4.50 ± 0.25]
0.177 ± 0.010
[4.50 ± 0.25]
0.220 ± 0.008
[5.59 ± 0.20]
0.220 ± 0.010
[5.59 ± 0.25]
WIDTH
0.063 ± 0.008
[1.60 ± 0.20]
0.098 ± 0.008
[2.50 ± 0.20]
0.080 ± 0.010
[2.03 ± 0.25]
0.126 ± 0.008
[3.20 ± 0.20]
0.252 ± 0.010
[6.40 ± 0.25]
0.200 ± 0.008
[5.08 ± 0.20]
0.250 ± 0.010
[6.35 ± 0.25]
MAXIMUM
THICKNESS (T)
0.067 [1.70]
TERMINATION PAD
MINIMUM
0.010 [0.25]
MAXIMUM
0.028 [0.71]
VJ1210
0.067 [1.70]
0.010 [0.25]
0.028 [0.71]
VJ1808
0.086 [2.18]
0.010 [0.25]
0.030 [0.76]
VJ1812
0.086 [2.18]
0.010 [0.25]
0.030 [0.76]
VJ1825
0.086 [2.18]
0.010 [0.25]
0.030 [0.76]
VJ2220
0.086 [2.18]
0.010 [0.25]
0.030 [0.76]
VJ2225
0.086 [2.18]
0.010 [0.25]
0.030 [0.76]
ORDERING INFORMATION
VJ1206
CASE
SIZE
1206
1210
1808
1812
1825
2220
2225
A
DIELECTRIC
101
CODE
A = C0G (NP0) Expressed in
picofarads (pF).
The first two
digits are
significant, the
third is a
multiplier.
Example:
101= 100 pF
J
TOLERANCE
F=±1%
G=±2%
H=±3%
J=±5%
K = ± 10 %
M = ± 20 %
X = Ni barrier
100 %Tinplate
matte finish
F = AgPd
B = Polymer
100 % Tinplate
matte finish
X
TERMINATION
B
DC VOLTAGE
RATING
A = 50 V
B = 100 V
C = 200 V
E = 500 V
L = 630 V
G = 1000 V
R = 1500 V
F = 2000 V
H = 3000 V
1)
A
MARKING
T
PACKAGING
##
2)
PROCESS
CODE
CAPACITANCE CAPACITANCE
A = Unmarked
T = 7" Reels
R = 11 1/4"
Reels
B = Bulk
W = Waffle
tray
4X = OMD
Cap
5H = OMD
Cap 100 %
voltage
condition
Notes:
1. DC voltage rating should not be exceeded in application
2. Process code with 2 digits has to be added
3. Polymer plus termination “B” termination part number code length dimensions positive tolerances (including bandwidth) above are allowed
to increase by the following amounts.
1210 and larger case sizes: Length 0.04 (0.1)
www.vishay.com
6
For technical questions, contact: mlcc.specials@vishay.com
Document Number 45047
Revision: 16-Aug-07
VJ OMD - C0G (NP0)
Surface Mount Multilayer Ceramic Chip Capacitor Solutions
Vishay Vitramon
for Boardflex Sensitive Applications
OMD - C0G (NP0) CAPACITANCE RANGE
EIA CODE
VOLTAGE (Vdc)
50
VJ1206
1)
VJ1210
1)
VJ1808
1)
100 200 500 630 1000 1500 2000 3000
100 200 500 630 1000 1500 50 100 200 500 630 1000 1500 2000 50
CAP.
CAP.
CODE
100
10 pF
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120
12 pF
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150
15 pF
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180
18 pF
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220
22 pF
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270
27 pF
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330
33 pF
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390
39 pF
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470
47 pF
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560
56 pF
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680
68 pF
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820
82 pF
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•
101
100 pF
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121
120 pF
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151
150 pF
181
180 pF
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•
•
•
•
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•
221
220 pF
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•
•
•
•
•
•
•
•
271
270 pF
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•
•
•
•
•
•
•
•
331
330 pF
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•
•
•
•
•
•
•
•
391
390 pF
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•
•
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•
•
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•
•
471
470 pF
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•
•
•
•
•
•
•
•
561
560 pF
•
•
•
•
•
•
•
•
•
681
680 pF
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•
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•
•
•
•
•
•
821
820 pF
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
102
1000 pF
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•
•
•
•
•
•
122
1200 pF
152
1500 pF
•
•
•
•
•
•
182
1800 pF
•
•
•
•
•
•
222
2200 pF
•
•
•
•
•
•
272
2700 pF
•
•
•
•
•
332
3300 pF
•
•
•
•
•
392
3900 pF
•
•
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•
472
4700 pF
•
•
•
•
562
5600 pF
•
682
6800 pF
•
822
8200 pF
•
103
0.010 µF
123
0.012 µF
153
0.015 µF
183
0.018 µF
223
0.022 µF
273
0.027 µF
333
0.033 µF
393
0.039 µF
473
0.047 µF
563
0.056 µF
683
0.068 µF
823
0.082 µF
104
0.1 µF
Note:
1. See soldering recommendations within this data book, or visit www.vishay.com/doc?45034
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Document Number 45047
Revision: 16-Aug-07
For technical questions, contact: mlcc.specials@vishay.com
www.vishay.com
7
VJ OMD - C0G (NP0)
Vishay Vitramon
Surface Mount Multilayer Ceramic Chip Capacitor Solutions
for Boardflex Sensitive Applications
OMD - C0G (NP0) CAPACITANCE RANGE
EIA CODE
VJ1812
1)
VJ1825
1)
VJ2220
1)
VJ2225
1)
VOLTAGE
50 100 200 500 630 1000 1500 2000 3000 50 100 200 500 630 1000 50 100 200 500 630 1000 50 100 200 500 630 1000
(VDC)
CAP.
CAP.
CODE
100
10 pF
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•
•
•
•
•
•
•
•
120
12 pF
•
•
•
•
•
•
•
•
•
150
15 pF
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•
•
•
•
•
•
•
•
•
180
18 pF
•
•
•
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•
•
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•
•
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•
220
22 pF
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•
•
•
•
•
•
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•
270
27 pF
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•
•
•
•
•
•
•
•
•
•
330
33 pF
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•
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•
•
•
390
39 pF
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•
•
•
•
•
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•
•
470
47 pF
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•
560
56 pF
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•
680
68 pF
•
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•
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•
•
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•
820
82 pF
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•
101
100 pF
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•
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•
121
120 pF
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•
•
151
150 pF
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•
181
180 pF
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•
221
220 pF
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•
•
•
•
•
•
271
270 pF
•
•
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•
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•
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•
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•
•
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•
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•
•
•
331
330 pF
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•
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•
•
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•
•
•
•
•
391
390 pF
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•
•
•
•
•
•
•
•
•
•
•
471
470 pF
•
•
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•
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•
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•
•
•
•
561
560 pF
•
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681
680 pF
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•
•
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•
821
820 pF
•
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•
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•
102 1000 pF
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•
122 1200 pF
•
152 1500 pF
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•
•
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•
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182 1800 pF
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222 2200 pF
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272 2700 pF
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332 3300 pF
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392 3900 pF
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472 4700 pF
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562 5600 pF
•
682 6800 pF
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822 8200 pF
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103 0.010 µF
•
123 0.012 µF
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153 0.015 µF
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183 0.018 µF
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223 0.022 µF
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273 0.027 µF
•
•
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333 0.033 µF
•
•
•
•
•
393 0.039 µF
•
•
•
473 0.047 µF
•
563 0.056 µF
683 0.068 µF
823 0.082 µF
104
0.1 µF
Note:
1. See soldering recommendations within this data book, or visit www.vishay.com/doc?45034
www.vishay.com
8
For technical questions, contact: mlcc.specials@vishay.com
Document Number 45047
Revision: 16-Aug-07
VJ OMD - C0G (NP0)
Surface Mount Multilayer Ceramic Chip Capacitor Solutions
Vishay Vitramon
for Boardflex Sensitive Applications
OMD - C0G (NP0) CAPACITORS - TYPICAL PARAMETERS
TEMPERATURE COEFFICIENT OF CAPACITANCE
2.0
10 000
% CAPACITANCE CHANGE
1.0
0.5
0.0
- 0.5
- 1.0
- 1.5
- 2.0
- 75 - 50
- 25
0
25
50
75
100 125
TEMPERATURE
°C
NP0
INSULATION RESISTANCE
(
Ω
FARADS)
1.5
MINIMUM INSULATION
RESISTANCE VS TEMPERATURE
1000
100
10
10
25
TEMPERATURE
°
C
100 125
AGING RATE - NP0
% CAPACITANCE CHANGE
0.2
% CAPACITANCE CHANGE
VOLTAGE COEFFICIENT OF CAPACITANCE - 1000V RATED
30
20
10
0
- 10
- 20
- 30
0.1
0.0
- 0.1
- 0.2
1
10
100
HOURS
1000
10 000
0
100 200 300
400 500
600 700
800
900 1000
DC VOLTS APPLIED
Document Number 45047
Revision: 16-Aug-07
For technical questions, contact: mlcc.specials@vishay.com
www.vishay.com
9
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ywchen03 Embedded System
STM8 UART problem
After the STM8's UART is initialized, data cannot be sent. Only after adding this function at the end of the routine can it be sent. I would like to ask the masters if there is any other operation req...
stonepal stm32/stm8
How to divide and connect analog ground and digital ground?
After reading some articles, I still have some questions about analog and digital ground. Please give me more advice. 1. The requirement of single-point grounding is to make single-point grounding at ...
mwl0223 Analog electronics
【GD32F350 Sharing】Simple Pedometer Design
[i=s]This post was last edited by hanyeguxingwo on 2018-9-22 13:57[/i] [align=center][color=#333333][font=Tahoma][b][size=4]Simple pedometer design[/size][/b][/font][/color][/align] [align=left][b][Po...
hanyeguxingwo GD32 MCU
Help with ARM300 issues
I encountered a very simple problem when doing a course project... But I couldn't solve it... My source code is as follows/*****************************************************************************...
eestudent ARM Technology
The vivado simulation output waveform signal input is all Z and the output is all X
Source file: `timescale 1ns / 1ps module clk_counter(inputsys_clk,inputrst_n,inputgate,output reg[31:0]clk_cnt,output regcounter_valid);always@(posedge sys_clk or negedge rst_n)beginif(rst_n == 1'b0)b...
1nnocent FPGA/CPLD
Shortcut:   S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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