Winbond CLOCK GENERATOR
W83195BR-120/W83195BG-120
For INTEL 915/945 Chipset
Date:
Jan./23/2006
Revision: 0.61
W83195BR-120/W83195BG-120
W83195BR-120 Data Sheet Revision History
Pages
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1-4,6,8,
10-15,18
1,3-8,
10,12,13
Dates
02/21/2005
03/25/2005
01/23/2006
Versi
on
0.5
0.6
0.61
Web
Version
n.a.
n.a.
n.a.
Main Contents
All of the versions before 0.50 are for internal
use.
Please see red text
Modify some description and add lead free part
number.
Please note that all data and specifications are subject to change without notice. All
the trademarks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
-I-
Publication Release Date: January 2006
Revision 0.61
W83195BR-120/W83195BG-120
Table of Content-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 1
PRODUCT FEATURES .............................................................................................................. 1
PIN CONFIGURATION ............................................................................................................... 2
BLOCK DIAGRAM ...................................................................................................................... 3
PIN DESCRIPTION..................................................................................................................... 4
5.1
5.2
5.3
5.4
5.5
5.6
6.
7.
Crystal I/O.................................................................................................................................4
CPU, SRC, and PCI_E, PCI, Clock Outputs...........................................................................4
Fixed Frequency Outputs.........................................................................................................5
I2C Control Interface ................................................................................................................5
Power Management Pins.........................................................................................................5
Power Pins................................................................................................................................6
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7
I2C CONTROL AND STATUS REGISTERS .............................................................................. 8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
Regisbit 0: Frequency Select (Default: 10h)............................................................................8
Register 1: CPU Clock Control (1 = Enable, 0 = Disable) (Default: E2h)...............................8
Register 2: PCI Clock Control (1 = Enable, 0 = Disable) (Default: FFh) ................................9
Register 3: PCI Clock Control (1 = Enable, 0 = Disable) (Default: FFh) ................................9
Register 4: 24_48MHz, 48MHz, REF Control (1 = Enable, 0 = Disable) (Default: FFh) .......9
Register 5: Watchdog Control (Default: 02h) ........................................................................10
Register 6: PCIE Control (1 = Enable, 0 = Disable) (Default: FEh)......................................10
Register 7: Winbond Chip ID (Default: 22h) (Read Only).....................................................11
Register 8: M/N Program (Default: 90h)................................................................................11
Register 9: M/N Program Register (Default: BBh) ................................................................11
Register 10: Reserved (Default: 3Bh)....................................................................................12
Register 11: Spread Spectrum Programming (Default: 0Eh) ...............................................12
Register 12: Divisor Control (Default: 08h)............................................................................12
Register 13: Step-less Enable Control (Default: 0Ah)...........................................................13
Register 14: Control (Default: 10h) ........................................................................................13
Register 15: SST Control (Default: ECh)...............................................................................14
Register 16: Skew Control (Default: E4h) .............................................................................14
Note: The skew rate control select bit fit value Please felloe below table............................14
Register 17: Slew rate Control (Default: 00h)........................................................................15
Register 18: Reserved (Default: 00h) ....................................................................................15
Register 19: Skew Control (Default: DAh).............................................................................15
Register 20: Watch dog timer (Default: 88h).........................................................................16
-II-
W83195BR-120/W83195BG-120
7.23
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
10.
11.
12.
Register21: Asynchronous mode Control (Default: 4Bh)......................................................16
Block Write protocol ...............................................................................................................17
Block Read protocol ...............................................................................................................17
Byte Write protocol .................................................................................................................17
Byte Read protocol.................................................................................................................17
ABSOLUTE MAXIMUM RATINGS .......................................................................................18
General Operating Characteristics ........................................................................................18
Skew Group timing clock........................................................................................................18
CPU 0.7V Electrical Characteristics ......................................................................................19
SRC 0.7V Electrical Characteristics ......................................................................................19
PCIE 0.7V Electrical Characteristics......................................................................................20
PCI Electrical Characteristics.................................................................................................20
24M, 48M Electrical Characteristics ......................................................................................20
REF Electrical Characteristics ...............................................................................................21
DOT 0.7V Electrical Characteristics ......................................................................................21
ACCESS INTERFACE .............................................................................................................. 17
SPECIFICATIONS .................................................................................................................... 18
ORDERING INFORMATION..................................................................................................... 22
HOW TO READ THE TOP MARKING...................................................................................... 22
PACKAGE DRAWING AND DIMENSIONS.............................................................................. 23
- III -
Publication Release Date: January 2006
Revision 0.61
W83195BR-120/W83195BG-120
1. GENERAL DESCRIPTION
The W83195BR-120 is a Clock Synthesizer for Intel 915/945 chipsets. W83195BR-120 provides all
clocks required for the high-speed microprocessor and provides step-less frequency programming and
32 different frequencies of CPU, PCI, and PCI-E clocks setting, support SRC 100MHz for SATA and
DOT 96MHz clock outputs, all clocks are externally selectable with smooth transitions.
The W83195BR-120 provides I
2
C serial bus interface to program the registers to enable or disable
each clock outputs and provides -0.5% down type spread spectrum or programmable S.S.T. scale to
reduce EMI.
The W83195BR-120 also has watchdog timer and reset output pin to support auto-reset when
systems stop functioning caused by improper frequency setting.
The W83195BR-120 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
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2 pair 0.7 V current mode Differential clock outputs for CPU.
1 pair 0.7V current mode Differential clock 100MHz outputs for SRC.
1 pair 0.7V current mode Differential 96MHz clock outputs for DOT.
6 pair 0.7V current mode Differential clock outputs for PCI-Express.
1 pair 0.7 V current mode Differential clock outputs select for CPUCLK_ITP.
7 PCI synchronous clocks include 3 PCI clock free running.
1 24_48Mhz clock output for super I/O.
1 48 MHz clock output for USB.
1 14.318MHz REF clock outputs.
Smooth frequency switch with selections from 100 to 400MHz.
Step-less frequency programming.
I
2
C 2-wire serial interface and support byte read/write and block read/write.
-0.5% down type spread spectrum in H/W and software select mode.
Programmable S.S.T. scale to reduce EMI in M/N mode.
Programmable registers to enable/disable each output and select modes.
Programmable clock outputs slew rate control and skew control.
Watch Dog Timer and RESET# output pins.
•
56 pin SSOP package.
-1-
Publication Release Date: January 2006
Revision 0.61
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