23A256/23K256
256K SPI Bus Low-Power Serial SRAM
Device Selection Table
Part Number
23K256
23A256
V
CC
Range
2.7-3.6V
1.7-1.95V
Page Size
32 Byte
32 Byte
Temp. Ranges
I
I
Packages
P, SN, ST
P, SN, ST
Features:
• Max. Clock 20 MHz
• Low-Power CMOS Technology:
- Read Current: 3 mA at 1 MHz
- Standby Current: 4
μA
Max. at 3.6V
• 32,768 x 8-bit Organization
• 32-Byte Page
• HOLD pin
• Flexible Operating modes:
- Byte read and write
- Page mode (32 Byte Page)
- Sequential mode
• Sequential Read/Write
• High Reliability
• Temperature Ranges Supported:
- Industrial (I):
-40°C to +85°C
• Pb-Free and RoHS Compliant, Halogen Free
Description:
The Microchip Technology Inc. 23X256 are 256 Kbit
Serial SRAM devices. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 23X256 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead TSSOP.
Package Types (not to scale)
Pin Function Table
Name
CS
SO
V
SS
SI
SCK
HOLD
V
CC
Function
Chip Select Input
Serial Data Output
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
CS
SO
NC
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC/TSSOP
(P, SN, ST)
©
2008 Microchip Technology Inc.
Preliminary
DS22100B-page 1
23A256/23K256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................4.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+0.3V
Storage temperature .................................................................................................................................-40°C to 125°C
Ambient temperature under bias .................................................................................................................-40°C to 85°C
ESD protection on all pins ...........................................................................................................................................2kV
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Min.
1.7
2.7
.7 V
CC
-0.3
—
V
CC
-0.5
—
—
—
—
—
—
Standby current
—
1
4
7
—
1.2
—
μA
pF
V
Typ
(1)
—
—
—
—
—
—
—
—
—
—
—
200
T
A
= -40°C to +85°C
Max.
1.95
3.6
V
CC
+0.3
0.2xV
CC
0.2
—
±0.5
±0.5
3
6
10
500
Units
V
V
V
V
V
V
μA
μA
mA
mA
mA
nA
I
OL
= 1 mA
I
OH
= -400
μA
CS = V
CC
, V
IN
= V
SS OR
V
CC
CS = V
CC
, V
OUT
= V
SS OR
V
CC
F
CLK
= 1 MHz; SO = O
F
CLK
= 10 MHz; SO = O
F
CLK
= 20 MHz; SO = O
CS = V
CC
= 1.8V, Inputs tied to V
CC
or V
SS
CS = V
CC
= 3.0V, Inputs tied to V
CC
or V
SS
V
CC
= 0V, f = 1 MHz, Ta = 25°C
(Note 1)
23A256
23K256
Test Conditions
DC CHARACTERISTICS
Param.
No.
D001
D001
D002
D003
D004
D005
D006
D007
D008
Sym.
V
CC
V
CC
V
IH
V
IL
V
OL
V
OH
I
LI
I
LO
I
CC
Read
Operating current
D009
I
CCS
Characteristic
Supply voltage
Supply voltage
High-level input
voltage
Low-level input
voltage
Low-level output
voltage
High-level output
voltage
Input leakage
current
Output leakage
current
D010
D011
Note 1:
2:
C
INT
V
DR
Input capacitance
RAM data retention
voltage
(2)
This parameter is periodically sampled and not 100% tested. Typical measurements taken at room
temperature (25°C).
This is the limit to which V
DD
can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
DS22100B-page 2
Preliminary
©
2008 Microchip Technology Inc.
23A256/23K256
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
2.3
Read Sequence
The 23X256 is a 32,768-byte Serial SRAM designed to
interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC
®
microcontrollers. It
may also interface with microcontrollers that do not
have a built-in SPI port by using discrete I/O lines
programmed properly in firmware to match the SPI
protocol.
The 23X256 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 23X256 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
The device is selected by pulling CS low. The 8-bit
READ
instruction is transmitted to the 23X256 followed
by the 16-bit address, with the first MSB of the address
being a “don’t care” bit. After the correct
READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
If operating in Page mode, after the first byte of data is
shifted out, the next memory location on the page can
be read out by continuing to provide clock pulses. This
allows for 32 consecutive address reads. After the
32nd address read the internal address counter wraps
back to the byte 0 address in that page.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (7FFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS pin
(Figure 2-1).
2.2
Modes of Operation
2.4
Write Sequence
The 23A256/23K256 has three modes of operation that
are selected by setting bits 7 and 6 in the STATUS
register. The modes of operation are Byte, Page and
Burst.
Byte Operation
– is selected when bits 7 and 6 in the
STATUS register are set to
00.
In this mode, the read/
write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next 8 clocks (Figure 2-1, Figure 2-2).
Page Operation
– is selected when bits 7 and 6 in the
STATUS register are set to
10.
The 23A256/23K256 has
1024 pages of 32 Bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure 2-3, Figure 2-4).
Sequential Operation
– is selected when bits 7 and 6
in the STATUS register are set to
01.
Sequential opera-
tion allows the entire array to be written to and read
from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x0000
(Figure 2-5, Figure 2-6).
Prior to any attempt to write data to the 23X256, the
device must be selected by bringing CS low.
Once the device is selected, the Write command can
be started by issuing a
WRITE
instruction, followed by
the 16-bit address, with the first MSB of the address
being a “don’t care” bit, and then the data to be written.
A write is terminated by the CS being brought high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 Bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is automati-
cally incremented. When the Address Pointer reaches
the highest address (7FFFh), the address counter rolls
over to (0000h). This allows the operation to continue
indefinitely, however, previous data will be overwritten.
©
2008 Microchip Technology Inc.
Preliminary
DS22100B-page 5
京公网安备 11010802033920号
EEWORLD
