Z8913620VSC datasheet, PDF - EEWORLD Datasheet

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Z8913620VSC: DescriptionMixed Signal Processor, 8-Bit Size, 8-Ext Bit, 20.48MHz, CMOS, PQCC68, PLASTIC, LCC-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size325KB，66 Pages; ManufacturerZilog, Inc.; Websitehttps://www.zilog.com/

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Z8913620VSC Overview

Mixed Signal Processor, 8-Bit Size, 8-Ext Bit, 20.48MHz, CMOS, PQCC68, PLASTIC, LCC-68

Z8913620VSC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zilog, Inc.
Parts packaging code	LCC
package instruction	PLASTIC, LCC-68
Contacts	68
Reach Compliance Code	unknow
Address bus width	16
barrel shifter	NO
bit size	8
boundary scan	NO
CPU series	Z8
maximum clock frequency	20.48 MHz
External data bus width	8
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
length	24.2316 mm
low power mode	YES
Number of terminals	68
Maximum operating temperature	55 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	1280
rom(word)	30720
ROM programmability	MROM
Maximum seat height	4.57 mm
speed	20.4 MHz
Maximum slew rate	40 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	24.2316 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, MIXED

Z8913620VSC Preview

RELIMINARY

RODUCT

PECIFICATION

Z89135/Z89136

-C

OST

DTAD C

ONTROLLER

FEATURES

Device

Z89135

Z89136

ROM

(KB)

RAM*

(Bytes)

256

I/O

Lines

Speed

(MHz)

Clock Speed of 20.48 MHz

16-Bit Digital Signal Processor (DSP)

6K Word DSP Program ROM

512 Words On-Chip DSP RAM

8-Bit A/D Converter with up to 128 kHz Sample Rate

10-Bit PWM D/A Converter (4 kHz to 64 kHz)

Three Vectored, Prioritized DSP Interrupts

Two DSP Timers to Support Different A/D and

D/A Sampling Rates

Z8 and DSP Operation in Parallel

IBM

PC-Based Development Tools

Developer’s Toolbox for T.A.M. Applications

24 KB of Z8 Program ROM (Z89135)

Watch-Dog Timer and Power-On Reset

Low Power STOP Mode

On-Chip Oscillator which Accepts a Crystal or External

Clock Drive

Two 8-Bit Z8 Counter Timers with 6-Bit Prescaler

Global Power-Down Mode

Low Power Consumption - 200 mW (typical)

Two Comparators with Programmable Interrupt Priority

Six Vectored, Priority Z8 Interrupts

RAM and ROM Protect

IBM is a registered trademark of International Business

Machines Corp.

GENERAL DESCRIPTION

The Z89135/136 is a fully integrated, dual processor con-

troller designed for low-cost digital telephone answering

machines. The I/O control processor is a Z8

MCU with 24

KB of program memory, two 8-bit counter/timers, and up to

47 I/O pins. The DSP is a 16-bit processor with a 24-bit

ALU and accumulator, 512 x 16 bits of RAM, single cycle

instructions, and 6K word program ROM plus constants

memory. The chip also contains a half-flash 8-bit A/D con-

verter with up to 128 kHz sample rate and 10-bit PWM D/A

converter. The sampling rates for the converters are pro-

grammable. The precision of the 8-bit A/D may be extend-

ed by resampling the data at a lower rate in software.

The Z8 and DSP processors are coupled by mailbox regis-

ters and an interrupt system, which allows DSP or Z8 pro-

grams to be directed by events in each other’s domain.

The Z89136 is the ROMless version of the Z89135. The

DSP is not ROMless. The DSP's program memory is al-

ways the internal ROM.

DS97TAD0300

PRELIMINARY

1-1

Z89135/136 (ROMless)

Low-Cost DTAD Controller

Zilog

GENERAL DESCRIPTION

(Continued)

Address

or I/O

(Nibble

Programmable)

P00

P01

P02

P03

Port 0

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

Timer 0

Capture Reg.

Timer 1

256 x 8 Bit

Port 3

P31

P32

P33

Input

24 Kbytes

Program

ROM

(Z89165)

Internal Address Bus

Z8 Core

Internal Data Bus

Expanded

Port 4

P34

P35 Output

P36

P37

P40

P41

P42

I/O

P43

(Bit

P44 Programmable)

P45

P46

P47

Address/Data

or I/O

(Byte

Programmable)

Port 1

Expanded Register

File

(Z8)

Peripheral

(DSP)

Extended Bus of the DSP

mailbox

Port 2

256 Word

RAM 0

256 Word

RAM 1

Port 5

I/O

(Bit

Programmable)

Internal Address Bus

6K Words

Program

ROM

Internal Data Bus

INT 1

DSP Core

P50

P51

P52

P53

P54

P55

P56

P57

I/O

(Bit

Programmable)

RMLS

/AS

/DS

R/W

XTAL1

XTAL2

VDD

GND

/RESET

INT 2

Ext.

Memory

Control

DSP Port

Extended Bus of the DSP

Timer 2

Timer 3

PWM

(10-Bit)

OSC

DSP0

DSP1

PWM

Power

ADC

(8-Bit)

AN IN

AN VDD

AN GND

VREF+

VREF-

Figure 1. Functional Block Diagram

1-2

PRELIMINARY

DS97TAD0300

Zilog

Z89135/136 (ROMless)

Low-Cost DTAD Controller

Z8 Core Processor

The Z8 is Zilog’s 8-bit MCU core with an Expanded Regis-

ter File to allow access to register-mapped peripheral and

I/O circuits. The Z8

MCU offers a flexible I/O scheme, an

efficient register and address space structure, and a num-

ber of ancillary features.

For applications demanding powerful I/O capabilities, the

Z89135/136 offers 47 pins dedicated to input and output.

These lines are grouped into six ports. Each port is config-

urable under software control to provide timing, status sig-

nals and parallel I/O with or without handshake.

There are four basic memory resources for the Z8 that are

available to support a wide range of configurations: Pro-

gram Memory, Register File, Data Memory, and Expanded

an efficient register file that allows any of 256 on-board

data and control registers to be the source and/or the des-

tination of almost any instruction. Traditional microproces-

sor accumulator bottlenecks are eliminated.

The Register File is composed of 236 bytes of general-pur-

pose registers, four I/O port register,s and 15 control and

status registers. The Expanded Register File consists of

mailbox registers, WDT mode register, DSP Control regis-

ter, Stop-Mode Recovery register, Port Configuration reg-

ister, and the control and data registers for Port 4 and Port

To unburden the software from supporting the real-time

problems, such as counting/timing and data communica-

tion, the Z8 offers two on-chip counter/timers with a large

number of user selectable modes.

Watch-Dog Timer and Stop-Mode Recovery features are

software driven by setting specific bits in control registers.

STOP and HALT instructions support reduced power op-

eration. The low power STOP Mode allows parameter in-

formation to be stored in the register file if power fails. An

external capacitor or battery retains power to the device.

DSP Coprocessor

The DSP coprocessor is a second generation, 16-bit two’s

complement CMOS Digital Signal Processor (DSP). Most

instructions, including multiply and accumulate, are ac-

complished in a single clock cycle. The processor contains

two on-chip data RAM blocks of 256 words, a 6K word pro-

gram ROM, 24-bit ALU, 16 x 16 multiplier, 24-bit Accumu-

lator, shifter, six-level stack, three vectored interrupts, and

two inputs for conditional program jumps. Each RAM block

contains a set of four pointers which may be incremented

or decremented automatically to affect hardware looping

without software overhead. The data RAMs can be simul-

taneously addressed and loaded to the multiplier for a true

single cycle scalar multiply.

Four external DSP registers are mapped into the expand-

ed register file of the Z8. Communication between the Z8

and the DSP occurs through those common registers

which form the mailbox registers.

The analog signal is generated by a 10-bit resolution Pulse

Width Modulator. The PWM output is a digital signal with

CMOS output levels. The output signal has a resolution of

1 in 1024 with a sampling rate of 16 kHz (XTAL = 20.48

MHz). The sampling rate can be changed under software

control and can be set at 4, 10, 16, and 64 kHz. The dy-

namic range of the PWM is from 0 to 4V.

An 8-bit resolution half-flash A/D converter is provided.

The conversion is conducted with a sampling frequency of

8, 16, 32, 64, or 128 kHz. (XTAL = 20.48 MHz) in order to

provide oversampling. The input signal is 4V peak to peak.

Scaling is normally

1.25V for the 2.5V peak to peak off-

set.

Two additional timers (Timer2 and Timer3) have been

added to support different sampling rates for the A/D and

D/A converters. These timers are free running counters

that divide the crystal frequency to the appropriate sam-

pling of frequency.

Notes:

All signals with a preceding front slash, "/", are ac-

tive Low. For example, B//W (WORD is active Low); /B/W

(BYTE is active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Power

Ground

Circuit

GND

Device

DS97TAD0300

PRELIMINARY

1-3

Z89135/136 (ROMless)

Low-Cost DTAD Controller

Zilog

XTAL2

XTAL1

P22

P56

P23

P55

P54

GND

P17

P05

P24

P16

P25

P15

P26

P27

N/C

68 67 66 65 64 63 62 61

ANVDD

RMLS

GND

VDD

P00

P01

P02

P03

P57

P50

P04

P51

P52

P21

P20

P07

/DS

VREF+

ANIN

VREF-

ANGND

/AS

/RESET

R//W

PWM

P10

P47

P11

P46

P53

P45

P44

P43

N/C

Z89135

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

P31

P32

P33

P34

P35

P14

P36

P13

P37

P40

P12

P06

P41

DSP1

Figure 2. Z89135 68-Pin PLCC Pin Assignments

1-4

PRELIMINARY

DSP0

VDD

P42

DS97TAD0300

Zilog

Table 1. Z89135 68-Pin Plastic Leaded Chip Carrier,

Pin Identiﬁcation

Pin # Symbol Function

RMLS

P04

P50

P57

P03

P02

P01

P00

XTAL2

XTAL1

P22

P56

P23

P55

P54

GND

P17

P05

P24

P16

P25

P15

P26

P27

N/C

P31

P32

P33

P34

P35

P14

DSP1

ROMless

Power Supply

Port 0, Bit 4

Port 5, Bit 0

Port 5, Bit 7

Port 0, Bit 3

Port 0, Bit 2

Port 0, Bit 1

Port 0, Bit 0

Crystal Oscillator Clock

Port 2, Bit 2

Port 5, Bit 6

Port 2, Bit 3

Port 5, Bit 5

Port 5, Bit 4

Ground

Port 1, Bit 7

Port 0, Bit 5

Port 2, Bit 4

Port 1, Bit 6

Port 2, Bit 5

Port 1, Bit 5

Port 2, Bit 6

Port 2, Bit 7

Not Connected

Port 3, Bit 1

Port 3, Bit 2

Port 3, Bit 3

Port 3, Bit 4

Power Supply

Port 3, Bit 5

Port 1, Bit 4

DSP User Output 1

Direction

Control Input

Input/Output

Output

Input

Input/Output

Input

Output

Input/Output

Output

Z89135/136 (ROMless)

Low-Cost DTAD Controller

Table 1. Z89135 68-Pin Plastic Leaded Chip Carrier,

Pin Identiﬁcation

Pin # Symbol Function

DSP0

P36

P13

P37

P40

P12

P06

P41

P42

N/C

P43

P44

P45

P53

P46

P11

P47

P10

PWM

R//W

/RESET

/AS

ANGND

REF-

REF+

ANV

GND

P07

P20

P21

P52

P51

/DS

DSP User Output 0

Port 3, Bit 7

Port 1, Bit 3

Port 3, Bit 7

Port 4, Bit 0

Port 1, Bit 2

Port 0, Bit 6

Port 4, Bit 1

Port 4, Bit 2

Not Connected

Port 4, Bit 3

Port 4, Bit 4

Port 4, Bit 5

Port 5, Bit 3

Port 4, Bit 6

Port 1, Bit 1

Port 4, Bit 7

Port 1, Bit 0

Pulse Width Modulator

Read/Write

Reset

Address Strobe

Analog Ground

Analog Voltage Ref.

Analog Input

Analog Voltage Ref.

Analog Power Supply

Ground

Port 0, Bit 7

Port 2, Bit 0

Port 2, Bit 1

Port 5, Bit 2

Port 5, Bit 1

Data Strobe

Input/Output

Output

Direction

Output

Input/Output

Output

Input/Output

Output

Input/Output

Output

Input

DS97TAD0300

PRELIMINARY

1-5

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Z8913620VSC Related Products

	Z8913620VSC	Z8913520VSC
Description	Mixed Signal Processor, 8-Bit Size, 8-Ext Bit, 20.48MHz, CMOS, PQCC68, PLASTIC, LCC-68	Mixed Signal Processor, 8-Bit Size, 8-Ext Bit, 20.48MHz, CMOS, PQCC68, PLASTIC, LCC-68
Is it Rohs certified?	incompatible	incompatible
Maker	Zilog, Inc.	Zilog, Inc.
Parts packaging code	LCC	LCC
package instruction	PLASTIC, LCC-68	PLASTIC, LCC-68
Contacts	68	68
Reach Compliance Code	unknow	unknown
Address bus width	16	16
barrel shifter	NO	NO
bit size	8	8
boundary scan	NO	NO
CPU series	Z8	Z8
maximum clock frequency	20.48 MHz	20.48 MHz
External data bus width	8	8
Format	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE
JESD-30 code	S-PQCC-J68	S-PQCC-J68
JESD-609 code	e0	e0
length	24.2316 mm	24.2316 mm
low power mode	YES	YES
Number of terminals	68	68
Maximum operating temperature	55 °C	55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ	LDCC68,1.0SQ
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240	240
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
RAM (bytes)	1280	1280
rom(word)	30720	30720
ROM programmability	MROM	MROM
Maximum seat height	4.57 mm	4.57 mm
speed	20.4 MHz	20.4 MHz
Maximum slew rate	40 mA	40 mA
Maximum supply voltage	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	24.2316 mm	24.2316 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, MIXED	DIGITAL SIGNAL PROCESSOR, MIXED

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