EEWORLDEEWORLDEEWORLD

Part Number

Search

SV13HA911MAATR1

Description
Ceramic Capacitor, Multilayer, Ceramic, 3000V, 20% +Tol, 20% -Tol, C0G, 30ppm/Cel TC, 0.00091uF, Through Hole Mount, 3020, RADIAL LEADED
CategoryPassive components    capacitor   
File Size222KB,3 Pages
ManufacturerAVX
Download Datasheet Parametric View All

SV13HA911MAATR1 Overview

Ceramic Capacitor, Multilayer, Ceramic, 3000V, 20% +Tol, 20% -Tol, C0G, 30ppm/Cel TC, 0.00091uF, Through Hole Mount, 3020, RADIAL LEADED

SV13HA911MAATR1 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAVX
package instruction, 3020
Reach Compliance Code_compli
ECCN codeEAR99
capacitance0.00091 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high9.14 mm
JESD-609 codee0
length7.62 mm
Manufacturer's serial numberSV
Installation featuresTHROUGH HOLE MOUNT
multi-layerYes
negative tolerance20%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
Package formRadial
method of packingTR
positive tolerance20%
Rated (DC) voltage (URdc)3000 V
seriesSV
size code3020
surface mountNO
Temperature characteristic codeC0G
Temperature Coefficient-/+30ppm/Cel ppm/°C
Terminal surfaceTin/Lead (Sn/Pb)
Terminal pitch5.08 mm
Terminal shapeWIRE
width5.08 mm
High Voltage MLC Radials (SV Style)
Application Information on High Voltage MLC Capacitors
High value, low leakage and small size are difficult parameters
to obtain in capacitors for high voltage systems. AVX special
high voltage MLC radial leaded capacitors meet these
performance characteristics. The added advantage of these
capacitors lies in special internal design minimizing the electric
field stresses within the MLC. These special design criteria
result in significant reduction of partial discharge activity within
the dielectric and having, therefore, a major impact on long-
term reliability of the product. The SV high voltage radial
capacitors are conformally coated with high insulation
resistance, high dielectric strength epoxy eliminating the
possibility of arc flashover.
The SV high voltage radial MLC designs exhibit low ESRs at
high frequency. The same criteria governing the high voltage
design carries the added benefits of extremely low ESR in
relatively low capacitance and small packages. These
capacitors are designed and are ideally suited for applications
such as snubbers in high frequency power converters,
resonators in SMPS, and high voltage coupling/DC blocking.
C0G Dielectric
General Specifications
Capacitance Range
10 pF to .15 μF
(+25°C, 1.0 ±0.2 Vrms at 1kHz,
for ≤100 pF use 1 MHz)
Capacitance Tolerances
±5%; ±10%; ±20%
Operating Temperature Range
-55°C to +125°C
Temperature Characteristic
0 ± 30 ppm/°C
Voltage Ratings
600 VDC thru 5000 VDC (+125°C)
Dissipation Factor
0.15% max.
(+25°C, 1.0 ±0.2 Vrms at 1kHz,
for ≤100 pF use 1 MHz)
Insulation Resistance
(+25°C, at 500V)
100K MΩ min. or 1000 MΩ-μF min.,
whichever is less
Insulation Resistance
(+125°C, at 500V)
10K MΩ min., or 100 MΩ-μF min.,
whichever is less
Dielectric Strength
120% rated voltage, 5 seconds
Life Test
100% rated and +125°C
X7R Dielectric
General Specifications
Capacitance Range
100 pF to 2.2 μF
(+25°C, 1.0 ±0.2 Vrms at 1kHz)
Capacitance Tolerances
±10%; ±20%; +80%, -20%
Operating Temperature Range
-55°C to +125°C
Temperature Characteristic
±15% (0 VDC)
Voltage Ratings
600 VDC thru 5000 VDC (+125°C)
Dissipation Factor
2.5% max.
(+25°C, 1.0 ±0.2 Vrms at 1kHz)
Insulation Resistance
(+25°C, at 500V)
100K MΩ min., or 1000 MΩ-μF min.,
whichever is less
Insulation Resistance
(+125°C, at 500V)
10K MΩ min., or 100 MΩ-μF min.,
whichever is less
Dielectric Strength
120% rated voltage, 5 seconds
Life Test
100% rated and +125°C
74
The sadness and helplessness of a female programmer
The sadness and helplessness of a female programmer. To be honest, I am really tired. I work hard and hard, struggle with men, stay up late and work overtime until the early morning, and am exhausted ...
tiankai001 Talking
Startup Code
Can anyone explain what this code means?IF :DEF:__MICROLIBEXPORT __initial_spEXPORT __heap_baseEXPORT __heap_limitELSEIMPORT __use_two_region_memoryEXPORT __user_initial_stackheap__user_initial_stackh...
xinbako stm32/stm8
Understanding of FPGA DCM clock management unit
Looking at the Xilinx Datasheet, you will notice that Xilinx FPGAs do not have PLLs. In fact, DCM is a time management unit. ----------------------------------------------------- [b]DCM Overview[/b] D...
sadlife1000 FPGA/CPLD
TI Electronic Design Contest --- TI Component Comparison Table for Electronic Contest
TI Electronic Design Contest --- TI Component Comparison Table for Electronic Contest[[i] This post was last edited by qwqwqw2088 on 2013-7-11 23:13 [/i]]...
qwqwqw2088 Analogue and Mixed Signal
ADC0 and ADC1 sample signals separately, how to write interrupts? [LM3S]
Should the base addresses of ADC be ADC0_BASE andADC1_BASE respectively, or should they be unified asADC_BASE? Also, should interrupts be written for both modules or just one? I'm a little dizzy after...
喜鹊王子 Microcontroller MCU
CAM Training Manual
Practical Information---CAM Training Manual...
frozenviolet Industrial Control Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 585  2224  1142  1597  2217  12  45  23  33  2 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号