IDTCSPT857DPF8 datasheet, PDF - EEWORLD Datasheet

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IDTCSPT857DPF8: DescriptionPLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, TVSOP-48; Categorylogic logic; File Size139KB，15 Pages; ManufacturerIDT (Integrated Device Technology)

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IDTCSPT857DPF8 Overview

PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, TVSOP-48

IDTCSPT857DPF8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	TSSOP,
Contacts	48
Reach Compliance Code	compli
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	9.7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	48
Actual output times	10
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm
minfmax	220 MHz

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IDTCSPT857D

2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2.5V - 2.6V PHASE LOCKED

LOOP DIFFERENTIAL 1:10

SDRAM CLOCK DRIVER

FEATURES:

DESCRIPTION:

IDTCSPT857D

ADVANCE

INFORMATION

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR (Double Data Rate)

SDRAM applications requiring improved output crosspoint

voltage

• Operating frequency: 60MHz to 220MHz

• Very low skew:

– <100ps for PC1600 - PC2700

– <75ps for PC3200

• Very low jitter:

– <75ps for PC1600 - PC2700

– <50ps for PC3200

• 2.5V AV

and 2.5V V

DDQ

for PC1600-PC2700

• 2.6V AV

and 2.6V V

DDQ

for PC3200

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-

pin VFBGA packages

The CSPT857D is a PLL based clock driver that acts as a zero delay buffer

to distribute one differential clock input pair(CLK,

CLK

) to 10 differential output

pairs (Y

[0:9]

, Y

[0:9]

) and one differential pair of feedback clock output (FBOUT,

FBOUT).

External feedback pins (FBIN,

FBIN)

for synchronization of the

outputs to the input reference is provided. A CMOS Enable/Disable pin is

available for low power disable. When the input frequency falls below

approximately 20MHz, the device will enter power down mode. In this mode,

the receivers are disabled, the PLL is turned off, and the output clock drivers

are tristated, resulting in a current consumption of less than 200µA.

The CSPT857D requires no external components and has been optimised

for very low I/O phase error, skew, and jitter, while maintaining frequency and

duty cycle over the operating voltage and temperature range. The CSPT857D,

designed for use in both module assemblies and system motherboard based

solutions, provides an optimum high-performance clock source.

The CSPT857D is available in Commercial Temperature Range (0°C to

+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering

Information for details.

APPLICATIONS:

• Meets or exceeds JEDEC standard JESD 82-1A for registered

DDR clock driver

• Meets proposed DDR1-400 specification

• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),

PC2700 (DDR333), PC3200 (DDR400)

• Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,

SSTVF16859, SSTVN16859, DDR1 register, provides complete

solution for DDR1 DIMMs

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2003

Integrated Device Technology, Inc.

OCTOBER 2003

DSC-6835/2

IDTCSPT857DPF8 Related Products

	IDTCSPT857DPF8	IDTCSPT857DBVGI	IDTCSPT857DBVI8	IDTCSPT857DNLGI	IDTCSPT857DPAI8
Description	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, TVSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PBGA56, VFBGA-56	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PBGA56, VFBGA-56	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLASTIC, VFQFN-40	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-48
Is it Rohs certified?	incompatible	conform to	incompatible	conform to	incompatible
Parts packaging code	SOIC	BGA	BGA	QFN	TSSOP
package instruction	TSSOP,	VFBGA-56	VFBGA-56	HVQCCN, LCC40,.24SQ,20	TSSOP, TSSOP48,.3,20
Contacts	48	56	56	40	48
Reach Compliance Code	compli	compliant	not_compliant	unknown	not_compliant
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	R-PDSO-G48	R-PBGA-B56	R-PBGA-B56	S-PQCC-N40	R-PDSO-G48
JESD-609 code	e0	e1	e0	e3	e0
length	9.7 mm	7 mm	7 mm	6 mm	12.5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1	1
Number of terminals	48	56	56	40	48
Actual output times	10	10	10	10	10
Maximum operating temperature	70 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TFBGA	TFBGA	HVQCCN	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225	260	225	260	240
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns	0.075 ns	0.075 ns	0.075 ns	0.075 ns
Maximum seat height	1.2 mm	1.05 mm	1.05 mm	1 mm	1.1 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN LEAD	TIN SILVER COPPER	Tin/Lead (Sn/Pb)	Matte Tin (Sn) - annealed	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	BALL	BALL	NO LEAD	GULL WING
Terminal pitch	0.4 mm	0.65 mm	0.65 mm	0.5 mm	0.5 mm
Terminal location	DUAL	BOTTOM	BOTTOM	QUAD	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30
width	4.4 mm	4.5 mm	4.5 mm	6 mm	6.1 mm
minfmax	220 MHz	220 MHz	220 MHz	220 MHz	220 MHz
MaximumI(ol)	-	0.012 A	0.012 A	0.012 A	0.012 A
Humidity sensitivity level	-	3	3	3	1
Encapsulate equivalent code	-	BGA56,6X10,25	BGA56,6X10,25	LCC40,.24SQ,20	TSSOP48,.3,20
power supply	-	2.5 V	2.5 V	2.5 V	2.5 V
Base Number Matches	-	1	1	1	1

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