CM8500A
3A B
US
T
ERMINATOR
GENERAL DESCRIPTION
The CM8500A is a switching regulator designed to provide a
desired output voltage or termination voltage for various
applications by converting voltage supplies ranging from 2.0V
to 5.0V. The CM8500A can be implemented to produce
regulated output voltages in two different modes. In the
default mode, when the VIN/2 pin is open, the output voltage
is 50% of the VCCQ. The CM8500A can also be used to
produce various user-defined voltages by forcing a voltage on
the VIN/2 pin. In this case, the output voltage follows the
VIN/2 pin input voltage. The switching regulator is capable of
sourcing or sinking up to 3A of current while regulating an
output V
TT
voltage to within 3% or less.
The CM8500A, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs.
The voltage output of the regulator can be used as a
termination voltage for other bus interface standards such as
SSTL, CMOS, Rambus ™ ,GTL+, VME, LV-CMOS, LV-TTL,
and PECL.
FEATURES
Patent Filed #6,452,366
16 pin PTSSOP and PSOP package
Source and sink up to 3A, no heat sink required
Peak Current to 6A
Integrated Power MOSFETs
Output voltage can be programmed by external resistors
Separate voltages for VCCQ and PVDD
V OUT of ±3% or less at 3A
Minimum external components
Shutdown for standby or suspend mode operation
Thermal shutdown protection
6A Low Noise Current Limit Protection
External Soft Start
Rail to Rail output Buck Converter
APPLICATIONS
Mother Board
PCI / AGP Graphics
Game / Play Station
Set Top Box
IPC
SCSI-III Bus terminator
Buck Converter
PIN CONFIGURATION
PSOP-16 (PS16)/PTSSOP-16 (PT16)
Top View
1
2
3
4
5
6
7
8
VCC2
PVDD2
VL2
PGND2
AGND
VFB
VCCQ
AGND
16
15
14
13
12
11
10
9
VCC1
PVDD1
VL1
PGND1
AGND
SD
VIN/2
AGSEN
2004/12/20
Champion Microelectronic Corporation
Page 1
CM8500A
3A B
US
T
ERMINATOR
PIN DESCRIPTION
Pin No.
1,16
2,15
3,14
4,13
5,9,12
8
6
Symbol
VCC1,VCC2
PVDD1,PVDD2
VL1,VL2
PGND1,PGND2
AGND
Description
Voltage supply for internal circuits
Voltage supply for output power transistors
Output voltage/inductor connection (IDD1+IDD2,
Output RMS current)
Ground for output power transistors
Ground for internal reference voltage divider
Ground for remote sensing
Shutdown active high. CMOS input level
0.75 X
VCC
7
10
11
VIN/2
VCCQ
VFB
Input for external reference voltage
Voltage reference for external voltage divider
Feedback node for the V
TT
0
VCC +
0.3V
VIN
5
5
V
V
V
V
Min.
2
2
-3
Operating Rating
Typ.
Max.
2.5
2.5
5
5
3
Unit
V
V
A
AGSEN
SD
BLOCK DIAGRAM
VCCQ
10
VCC1
1
VCC2
16
SD
6
PVDD1
2
PVDD2
15
OSCILLATOR/
RAMP GENERATOR
3
VL1
14 VL2
S
Q
100K
ERROR AMP
-
R
+
RAMP AMP
COMPARATOR
Q
VIN/2
7
100K
+
-
AGND 5
AGND 9
20PF
AGND 12
8
AGND
11
VFB
4
PGND1
13
PGND2
ORDERING INFORMATION
Part Number
CM8500AIT
CM8500AIS
CM8500AGIT*
CM8500AGIS*
CM8500ATEVAL
*Note: G : Suffix for Pb Free Product
Temperature Range
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 85℃
16-Pin
16-Pin
16-Pin
16-Pin
Package
PTSSOP (PT16)
PSOP (PS16)
PTSSOP (PT16)
PSOP (PS16)
Evaluation Board (T16)
2004/12/20
Champion Microelectronic Corporation
Page 2
CM8500A
3A B
US
T
ERMINATOR
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the
device could be permanently damaged.
PVDD/VCC/VCCQ ......................................….......-0.3V to 6.0V
Voltage on Any Other Pin ………... GND – 0.3V to VCC + 0.3V
Output RMS Current, Source or Sink .....…………........…...3.0A
Junction Temperature ...…………………… …………150°C
Storage Temperature ……................……. -65°C to 125°C
Lead Temperature (Soldering, 5 sec)……………….. 260°C
Thermal Resistance(
θ
JA
)….. ………………….. .40°C/W
OPERATING CONDITIONS
Temperature Range ............................. -40°C to 85°C
P
VDD
Operating Range .........................2.0V to 5.0V
(Unless otherwise stated, these specifications apply T
A
=25°C;
VCC=+3.3V and PVDD=+3.3V)
maximum ratings are stress ratings only and functional device operation is not implied.(Note 1)
CM8500A
Min.
1.12
1.22
1.32
1.09
1.19
1.28
1.139
1.238
1.337
510
Typ.
1.15
1.25
1.35
1.15
1.25
1.35
1.15
1.25
1.35
50
600
690
3
6
6
150
180
Max.
1.18
1.28
1.38
1.21
1.31
1.42
1.162
1.263
1.364
ELECTRICAL CHARACTERISTICS
Symbol
SWITCHING REGULATOR
Parameter
Test Conditions
Unit
IOUT = 0, VCCQ = 2.3V
V
IN
/2 =
open
Note 2
VL
Output Voltage, SSTL_2
IOUT =
±3A,
V
IN
/2 =
open
Note 3
V
IN
/2
Z
IN
fsw
I
OUT(RMS)
I
OUT(PEAK)
I
limit
MOSFETs
RDS
(ON)
SUPPLY
I
VCCA
I
PVDD
Quiescent Current
VFB = 1.4V
LC unconnected
VFB = 1.4V
LC unconnected
Drain to Source on-State Resistance
PVDD=5V
Internal Resistor Divider
V
IN
/2 Reference Pin Input Impedance
Switching Frequency
Maximum Output RMS Current
Maximum Output Peak Current
Current limit
IOUT = 0
Note 2
Note 2
VCCQ = 2.3V
VCCQ = 2.5V
VCCQ = 2.7V
VCCQ = 0
VCCQ = 2.7V
VCCQ = 2.5V
VCCQ = 2.7V
VCCQ = 2.3V
VCCQ = 2.5V
V
V
V
V
V
V
V
V
V
KΩ
KHz
A
A
A
mΩ
CM8500A
CM8500A
CM8500A
CM8500A
200
500
µA
µA
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions
Note 2:
VCC, PVDD = 3.3V ±10%
Note 3:
It’s not 100% test
2004/12/20
Champion Microelectronic Corporation
Page 3
CM8500A
3A B
US
T
ERMINATOR
FUNCTIONAL DESCRIPTION
The CM8500A is a switching regulator that is capable of
sinking and sourcing 3A of current without an external heat
sink. CM8500A uses a standard surface mount PTSSOP
and PSOP package with bottom metal exposed and the heat
can be piped through the bottom of the device and onto the
PCB.
Low Noise Current Limit:
CM3708A’s current limit is a low noise current limit. It increase
the system loop noise immunity while it is doing the current limit
protection for the system. The current limit is around 6A for the
normal 3A operation.
INPUTS
The CM8500A integrates power MOSFETs that are capable
of source and sink 3A of current while maintaining excellent
voltage regulation. The output voltage can be regulated within
3% or less by using the external feedback. Separate voltage
supply inputs have been added to fit applications with various
power supplies for the databus and power buses.
The input voltage pins (VCCQ or VIN/2) determine the output
voltages (VL1 or VL2). In the default mode, when the VIN/2 pin
is open, the output voltage is 50% of the VCCQ input.
If a specific voltage is forced at the VIN/2 pin, the output voltage
follows the voltage at the VIN/2 pin. VCCQ suggested
connecting to VCCQ of memory module for better tracking with
memory VCCQ.
VREF
The reference voltage could be ranged from 0V to VIN.
OTHER SUPPLY VOLTAGES
Several inputs are provided for the supply voltages: PVDD1,
PVDD2, VCC1, and VCC2.
OUPUTS
The output voltage pins (VL1, VL2) are tied to the databus,
address, or clock lines via an external inductor. Output voltage The PVDD1 and PVDD2 provide the power supply to the power
is determined by the VCCQ or VIN/2 inputs so it can be from
0V to VIN..
MOSFETs. VCC1 and VCC2 provide the voltage supply to the
logic section and internal error amplifiers.
Internal Power Switches:
CM3708A has been integrated 2 Power MOSFETs whose
RDS
(ON)
is around 100m Ohm each.
FEEDBACK
The VFB pin is an input that can be used for closed loop
compensation. This input is derived from the voltage output.
AGSEN pin is a contact node of internal resistor divider for
remote sense.
APPLICATIONS
USING THE CM8500A FOR SSTL BUS
TERMINATION
Figure 1 is the typical schematic of the CM8500ATEVAL that
shows the recommended approach for bus terminating
solutions for SSTL-2 bus. This circuit can be used in PC
memory and Graphics memory applications as shown in
Figure 2 and Figure 3.
Figure 4 shows the PCB layout of the CM8500ATEVAL.
Table 1details the key parameters of SSTL_2 specification.
Figure 5 shows two different approach of SSTL_2 Terminated
Output. (Refer to page 8 for detail description.)
2004/12/20
Champion Microelectronic Corporation
Page 4
CM8500A
3A B
US
T
ERMINATOR
APPLICATION CIRCUIT
NOTE:
J3:referance output provided from Vtt
J4:short :Demo kit on .
open:off(into shutdown mode)
J6:reference output provided from shunt regulator
Vref-OUT
J3
1
2
J5:pin1 ,pin2 short:Vtt = 1/2Vcc
C13
104
1
TP1
4
BNC
3
R8
100
When external voltage applied ,pin1,2 should be open
5
and pin2:connect to external voltage (+)
pin3:connect to external voltage (-)
D6
Vtt=1/2 external voltage
100uf/6.3V
100uf/6.3V
820uf/6.3V
L1
3.3uH
SK12
R6,R7(option circuit)forVttVOLTAGEADJUST
2
Vtt=(Vcc*R6)/R6+R7
VTT
J1
1
2
C3
104
C12
C11
C7
C2
104
D5
SK12
C15
10uf/6.3V
VDD
VCC
1
2
U1 CM8500A
VCC1
VDD1
VL1
VCC2
VDD2
VL2
16
15
14
13
VDD
VCC
R1
5R1
VDD
J2
DC-INPUT
1
2
2
C14
100uf/6.3V
3
C4
104
C5
104
1
R5
100k
4
C1
104
PGND1 PGND2
AGND1 AGND4
SD
2/VCC
FB
VCCQ
5
12
11
10
9
2
J5
C9
100uf/6.3V
C10
10uf/6.3V
C16
470uf/6.3V
6
J4ON/OFF
2
2
R7
7
3
1
R6
10k
C6
8
G-sense AGND3
IN/EXT
1
10k
1
102
R3 200k
1
2
1
R4
1k
2
C8
102
Figure 1. CM8500A Typical Application
(Schematic of CM8500ATEVAL)
2004/12/20
Champion Microelectronic Corporation
Page 5
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