EVALUATION
KIT
AVAILABLE
1
TC7660S
SUPER CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER
FEATURES
s
s
s
s
s
s
s
s
s
s
Oscillator boost from 10kHz to 45kHz
Converts +5V Logic Supply to
±
5V System
Wide Input Voltage Range .................... 1.5V to 12V
Efficient Voltage Conversion ......................... 99.9%
Excellent Power Efficiency ............................... 98%
Low Power Supply .............................. 80
µ
A @ 5 V
IN
Low Cost and Easy to Use
— Only Two External Capacitors Required
Available in Small Outline (SOIC) Package
Improved ESD Protection ..................... Up to 10kV
No External Diode Required for High Voltage
Operation
GENERAL DESCRIPTION
The TC7660S is a pin-compatible upgrade to the Indus-
try standard TC7660 charge pump voltage converter. It
converts a +1.5V to +12V input to a corresponding -1.5V to
-12V output using only two low-cost capacitors, eliminating
inductors and their associated cost, size and EMI. Added
features include an extended supply range to 12V, and a
frequency boost pin for higher operating frequency, allowing
the use of smaller external capacitors.
The on-board oscillator operates at a nominal frequency
of 10kHz. Frequency is increased to 45kHz when pin 1 is
connected to V+. Operation below 10kHz (for lower supply
current applications) is possible by connecting an external
capacitor from OSC to ground (with pin 1 open).
The TC7660S is available in both 8-pin DIP and 8-pin
small outline (SOIC) packages in commercial and extended
temperature ranges.
PIN CONFIGURATION
(DIP and SOIC)
8 V+
7 OSC
LOW
TC7660SCOA 6 VOLTAGE (LV)
TC7660SEOA
5 VOUT
2
3
ORDERING INFORMATION
Part No.
TC7660SCOA
TC7660SCPA
TC7660SEJA
TC7660SEOA
TC7660SEPA
TC7660SMJA
4
Package
8-Pin SOIC
8-Pin Plastic DIP
8-Pin CerDIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin CerDIP
Temperature
Range
0°C to +70°C
0°C to +70°C
– 40°C to +85°C
– 40°C to +85°C
– 40°C to +85°C
– 55°C to +125°C
Boost 1
CAP + 2
8 V+
7 OSC
Boost
1
CAP + 2
GND
CAP –
3
4
GND 3 TC7660SCPA 6 LOW
VOLTAGE (LV)
TC7660SEJA
CAP – 4 TC7660SEPA 5 VOUT
5
TC7660EV
Evaluation Kit for
Charge Pump Family
FUNCTIONAL BLOCK DIAGRAM
V + CAP +
8
BOOST
1
2
6
4
CAP –
OSC
7
RC
OSCILLATOR
÷2
VOLTAGE–
LEVEL
TRANSLATOR
LV
6
5
INTERNAL
VOLTAGE
REGULATOR
LOGIC
NETWORK
VOUT
7
TC7660S
3
GND
8
TC7660S-14 9/16/96
TELCOM SEMICONDUCTOR, INC.
4-69
SUPER CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
TC7660S
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ......................................................... +13V
LV, Boost, OSC Inputs
Voltage (Note 1) ......................... – 0.3V to (V
+
+0.3V)
for V
+
<5.5V
(V
+
– 5.5V) to (V
+
+0.3V)
for V
+
>5.5V
Current Into LV (Note 1) ....................... 20µA for V
+
>3.5V
Output Short Duration (V
SUPPLY
≤
5.5V) ......... Continuous
Power Dissipation (T
A
≤
70°C) (Note 2)
CerDIP ............................................................800mW
Plastic DIP ......................................................730mW
SOIC ............................................................... 470mW
Operating Temperature Range
C Suffix .................................................. 0°C to +70°C
E Suffix ............................................. – 40°C to +85°C
M Suffix ........................................... – 55°C to +125°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under "Absolute Maximum Ratings" may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS:
T
A
= +25°C, V
+
= 5V, C
OSC
= 0, Test Circuit (Figure 1), unless otherwise
indicated.
Symbol
I
+
Parameter
Supply Current
(Boost pin OPEN or GND)
Test Conditions
R
L
=
∞
0°C
≤
T
A
≤
+70°C
– 40°C
≤
T
A
≤
+85°C
– 55°C
≤
T
A
≤
+125°C
0°C
≤
T
A
≤
+70°C
– 40°C
≤
T
A
≤
+85°C
– 55°C
≤
T
A
≤
+125°C
Min
≤
T
A
≤
Max,
R
L
= 10 kΩ, LV Open
Min
≤
T
A
≤
Max,
R
L
= 10 kΩ, LV to GND
I
OUT
= 20mA
I
OUT
= 20mA, 0°C
≤
T
A
≤
+70°C
I
OUT
= 20mA, – 40°C
≤
T
A
≤
+85°C
I
OUT
= 20mA, – 55°C
≤
T
A
≤
+125°C
V
+
= 2V, I
OUT
= 3 mA, LV to GND
0°C
≤
T
A
≤
+70°C
– 55°C
≤
T
A
≤
+125°C
Pin 7 open; Pin 1 open or GND
Boost Pin = V
+
R
L
= 5 kΩ; Boost Pin Open
T
MIN
≤
T
A
≤
T
MAX
; Boost Pin Open
Boost Pin = V
+
R
L
=
∞
V
+
= 2V
V
+
= 5V
Min
—
—
—
—
—
—
—
3
1.5
—
—
—
—
—
—
—
—
96
95
—
99
—
—
Typ
80
—
—
—
—
—
—
—
—
60
70
70
105
—
—
10
45
98
98
88
99.9
1
100
Max
160
180
180
200
300
350
400
12
3.5
100
120
120
150
250
400
—
—
—
—
—
—
—
—
Unit
µA
I
+
Supply Current
(Boost pin = V
+
)
Supply Voltage Range, High
Supply Voltage Range, Low
Output Source Resistance
µA
V+
H
V
+
L
R
OUT
V
V
Ω
Ω
kHz
%
F
OSC
P
EFF
Oscillator Frequency
Power Efficiency
V
OUT
E
FF
Z
OSC
Voltage Conversion Efficiency
Oscillator Impedance
%
MΩ
kΩ
NOTES:
1. Connecting any input terminal to voltages greater than V
+
or less than GND may cause destructive latch-up. It is recommended that no
inputs from sources operating from external supplies be applied prior to "power up" of the TC7660S.
2. Derate linearly above 50°C by 5.5mW/°C.
4-70
TELCOM SEMICONDUCTOR, INC.
SUPER CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
TC7660S
Detailed Description
The TC7660S contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10
µF
polar-
ized electrolytic capacitors. Operation is best understood by
considering Figure 2, which shows an idealized voltage
inverter. Capacitor C
1
is charged to a voltage V
+
for the half
cycle when switches S
1
and S
3
are closed. (Note: Switches
S
2
and S
4
are open during this half cycle.) During the second
half cycle of operation, switches S
2
and S
4
are closed, with
S
1
and S
3
open, thereby shifting capacitor C
1
negatively by
V
+
volts. Charge is then transferred from C
1
negatively by V+
volts. Charge is then transferred from C
1
to C
2
, such that the
voltage on C
2
is exactly V
+
, assuming ideal switches and no
load on C
2
.
The four switches in Figure 2 are MOS power switches;
S
1
is a P-channel device, and S
2
, S
3
and S
4
are N-channel
devices. The main difficulty with this approach is that in
integrating the switches, the substrates of S
3
and S
4
must
always remain reverse-biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start-up, and under output short circuit
conditions (V
OUT
= V
+
), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latch-up.
This problem is eliminated in the TC7660S by a logic
network which senses the output voltage (V
OUT
) together
with the level translators, and switches the substrates of S
3
and S
4
to the correct level to maintain necessary reverse
bias.
V+
S1
S2
1
2
C2
VOUT = – VIN
C1
GND
S3
S4
3
Figure 2. Idealized Charge Pump Inverter
The voltage regulator portion of the TC7660S is an
integral part of the anti-latch-up circuitry. Its inherent voltage
drop can, however, degrade operation at low voltages. To
improve low-voltage operation, the “LV” pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V, the LV terminal must be left
open to ensure latch-up-proof operation and prevent device
damage.
4
Theoretical Power Efficiency
Considerations
In theory, a capacitive charge pump can approach
100% efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
5
V+
1
2
C1
10µF
+
3
4
8
7
IS
V+
(+5V)
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The TC7660S approaches these conditions for nega-
tive voltage multiplication if large values of C
1
and C
2
are
used.
Energy is lost only in the transfer of charge
between capacitors if a change in voltage occurs.
The
energy lost is defined by:
E = 1/2 C
1
(V
12
– V
22
)
V
1
and V
2
are the voltages on C
1
during the pump and
transfer cycles. If the impedances of C
1
and C
2
are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of R
L
, there will be a substantial difference in
voltages V
1
and V
2
. Therefore, it is desirable not only to
make C
2
as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C
1
in order to achieve maximum efficiency of operation.
4-71
6
TC7660S
6
5
COSC
*
IL
RL
VO
C2
10µF
7
+
NOTE:
For large values of C
OSC
(>1000pF), the values
of C
1
and C
2
should be increased to 100µF.
Figure 1. TC7660S Test Circuit
8
TELCOM SEMICONDUCTOR, INC.
SUPER CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
TC7660S
Dos and Don'ts
• Do not exceed maximum supply voltages.
• Do not connect the LV terminal to GND for supply
voltages greater than 3.5V.
• Do not short circuit the output to V
+
supply for voltages
above 5.5V for extended periods; however, transient
conditions including start-up are okay.
• When using polarized capacitors in the inverting mode,
the + terminal of C
1
must be connected to pin 2 of the
TC7660S and the + terminal of C
2
must be connected
to GND.
The output characteristics of the circuit in Figure 3 are
those of a nearly ideal voltage source in series with 70Ω.
Thus, for a load current of –10mA and a supply voltage of
+5V, the output voltage would be –4.3V.
The dynamic output impedance of the TC7660S is due,
primarily, to capacitive reactance of the charge transfer
capacitor (C
1
). Since this capacitor is connected to the
output for only 1/2 of the cycle, the equation is:
2
X
C
=
= 3.18Ω,
2πf C
1
where f = 10kHz and C
1
= 10µF.
Paralleling Devices
Simple Negative Voltage Converter
Figure 3 shows typical connections to provide a nega-
tive supply where a positive supply is available. A similar
scheme may be employed for supply voltages anywhere in
the operating range of +1.5V to +12V, keeping in mind that
pin 6 (LV) is tied to the supply negative (GND) only for supply
voltages below 3.5V.
V
1
C1
10µF
+
2
3
4
8
7
VOUT
*
+
C2
10µF
+
Any number of TC7660S voltage converters may be
paralleled to reduce output resistance (Figure 4). The reser-
voir capacitor, C
2
, serves all devices, while each device
requires its own pump capacitor, C
1
. The resultant output
resistance would be approximately:
R
OUT
=
R
OUT
(of TC7660S)
n (number of devices)
TC7660S
6
5
*
NOTES:
Figure 3. Simple Negative Converter
V+
1
2
C1
3
4
8
7
1
2
C1
3
4
8
7
RL
TC7660S
"1"
6
5
TC7660S
"n"
6
5
+
C2
Figure 4. Paralleling Devices Lowers Output Impedance
4-72
TELCOM SEMICONDUCTOR, INC.
SUPER CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
TC7660S
+
V
1
2
+
10µF
3
4
TC7660S
"1"
8
7
6
5
10µF
+
1
2
3
4
TC7660S
"n"
8
7
6
5
+
VOUT
*
10µF
1
2
*
NOTES:
3
1. V
OUT
= –n(V
+
) for 1.5V
≤
V
+
≤
12V
+
10µF
Figure 5. Increased Output Voltage by Cascading Devices
Cascading Devices
The TC7660S may be cascaded as shown (Figure 5) to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
V
OUT
= –n (V
IN
)
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be ap-
proximately the weighted sum of the individual TC7660S
R
OUT
values.
Changing the TC7660S Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
Pin 1, frequency boost pin may be connected to V
+
to
increase oscillator frequency to 45kHz from a nominal of
10kHz for an input supply voltage of 5.0 volts. The oscillator
may also be synchronized to an external clock as shown in
Figure 6. In order to prevent possible device latch-up, a 1kΩ
resistor must be used in series with the clock output. In a
V+
1
2
+
10µF
3
4
TC7660S
8
1 kΩ
7
6
5
+
10µF
VOUT
CMOS
GATE
V+
situation where the designer has generated the external
clock frequency using TTL logic, the addition of a 10kΩ pull-
up resistor to V
+
supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be
¹⁄₂
of the clock frequency. Output transitions occur on
the positive-going edge of the clock.
It is also possible to increase the conversion efficiency
of the TC7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, C
OSC
, as shown in
Figure 7. Lowering the oscillator frequency will cause an
undesirable increase in the impedance of the pump (C
1
) and
the reservoir (C
2
) capacitors. To overcome this, increase the
values of C
1
and C
2
by the same factor that the frequency
has been reduced. For example, the addition of a 100pF
capacitor between pin 7 (OSC) and pin 8 (V
+
) will lower the
oscillator frequency to 1kHz from its nominal frequency of
10kHz (a multiple of 10), and necessitate a corresponding
increase in the values of C
1
and C
2
(from 10µF to 100µF).
4
5
6
Positive Voltage Multiplication
The TC7660S may be employed to achieve positive
voltage multiplication using the circuit shown in Figure 8. In
this application, the pump inverter switches of the TC7660S
are used to charge C
1
to a voltage level of V
+
–V
F
(where V
+
is the supply voltage and V
F
is the forward voltage drop of
diode D
1
). On the transfer cycle, the voltage on C
1
plus the
supply voltage (V
+
) is applied through diode D
2
to capacitor
C
2
. The voltage thus created on C
2
becomes (2V
+
) – (2V
F
),
or twice the supply voltage minus the combined forward
voltage drops of diodes D
1
and D
2
.
The source impedance of the output (V
OUT
) will depend
on the output current, but for V
+
= 5V and an output current
of 10mA, it will be approximately 60Ω.
7
Figure 6. External Clocking
8
TELCOM SEMICONDUCTOR, INC.
4-73
Embedded System
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