UTRON
Rev. 1.7
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 40/35/30 mA (typical)
Standby : 2.5µA (typical) L-version
0.5µA (typical) LL-version
Power supply range : 2.7V to 3.6V
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20 mm TSOP-1
32-pin 8x13.4 mm STSOP
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L1024 is a 1,048,576-bit low power
CMOS static random access memory organized
as 131,072 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
Easy memory expansion is provided by using
two chip enable input.(
CE
1
,CE2) It is
particularly well suited for battery back-up
nonvolatile memory application.
The UT62L1024 operates from a single 2.7V~
3.6V power supply and all inputs and outputs
are fully TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
2048
×
512
MEMORY
ARRAY
A0-A16
DECODER
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
1
UTRON
Rev. 1.7
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
32
31
30
29
Vcc
A15
CE2
WE
A11
A9
A8
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
32
31
30
29
28
27
26
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
5
6
7
8
9
10
11
12
13
14
15
16
28
27
26
25
24
23
22
21
20
19
18
17
A13
A8
A9
A11
OE
A10
PDIP / SOP
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE
1
,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
UT62L1024
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
UT62L1024
25
24
23
22
21
20
19
18
17
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
TSOP-I/STSOP
P80033
2
UTRON
Rev. 1.7
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to Vss
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
solder
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
RATING
-0.5 to +4.6
0 to +70
-65 to +150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High -Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,
I
SB1
I
SB
,
I
SB1
I
CC ,
I
CC1
I
CC ,
I
CC1
I
CC ,
I
CC1
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, Ta = 0
℃
to +70
℃
)
PARAMETER
SYMBOL TEST CONDITION
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Leakage Current
I
IL
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current I
OL
V
SS
≦
V
I/O
≦
V
CC
CE
1
=V
IH
or CE2 = V
IL
or
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
V
OH
V
OL
I
CC
OE
= V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
Cycle time =Min. 100% Duty,
CE
1
=V
IL
, CE2 = V
IH
,
I
I/O
= 0mA
Cycle time = 1µs, 100% Duty,
.
CE
1
≦
0.2V,CE2
≧
V
CC
-0.2V,
I
I/O
= 0mA
CE
1
=V
IH
or CE2 = V
IL
CE
1
≧
V
CC
-0.2V or
.CE2
≦
0.2V
-L
-
LL
MIN. TYP. MAX. UNIT
2.0
-
V
CC
+0.5 V
- 0.5
-
0.6
V
-1
-
1
µA
-1
2.2
-
-
-
-
-
-
-
-
-
-
-
40
35
30
-
-
2.5
0.5
1
-
0.4
60
50
40
5
1.0
100
20*
40
10*
µA
V
V
mA
mA
mA
mA
mA
µA
µA
35
55
70
I
CC1
Standby Power
Supply Current
I
SB
I
SB1
*Those parameters are for reference only under 50℃
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
3
UTRON
Rev. 1.7
CAPACITANCE
(Ta=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
-
-
MAX.
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.4V to 2.4V
5ns
1.5V
C
L
=50pF, I
OH
/I
OL
=-1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , Ta = 0
℃
to +70
℃
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT62L1024-35 UT62L1024-55 UT62L1024-70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
35
-
55
-
70
-
ns
Address Access Time
t
AA
-
35
-
55
-
70
ns
Chip Enable Access Time
t
ACE1
, t
ACE2
-
35
-
55
-
70
ns
Output Enable Access Time
t
OE
-
25
-
30
-
35
ns
Chip Enable to Output in Low-Z
t
CLZ1
*, t
CLZ2
* 10
-
10
-
10
-
ns
Output Enable to Output in Low-Z t
OLZ
*
5
-
5
-
5
-
ns
Chip Disable to Output in High-Z
t
CHZ1
*, t
CHZ2
*
-
25
-
30
-
35
ns
Output Disable to Output in High-Z t
OHZ
*
-
25
-
30
-
35
ns
Output Hold from Address Change t
OH
5
-
5
-
5
-
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
SYMBOL
t
WC
t
AW
t
CW1
, t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
UT62L1024-35 UT62L1024-55 UT62L1024-70
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
35
30
30
0
25
0
20
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
15
MIN.
55
50
50
0
40
0
25
0
5
-
MAX. MIN.
-
70
-
60
-
60
-
0
-
45
-
0
-
30
-
0
-
5
20
-
MAX.
-
-
-
-
-
-
-
-
-
25
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
4
UTRON
Rev. 1.7
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
t
RC
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
1
, CE2 and
OE
Controlled)
(1,3,5,6)
t
RC
Address
CE1
t
ACE1
t
AA
CE2
t
ACE2
OE
t
CLZ1
t
CLZ2
Dout
HIGH-Z
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ1
t
CHZ2
HIGH-Z
Data Valid
Notes :
1.
WE
is HIGH for a read cycle.
2. Device is continuously selected
OE
,
CE
1
=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
CE
1
4.
OE
is low.
low
and CE2 high transition; otherwise t
AA
is the limiting parameter.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
5
Mobile and portable
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