MDU-3C-60 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> MDU-3C-60

MDU-3C-60: DescriptionActive Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8; Categorylogic logic; File Size65KB，1 Pages; ManufacturerData Delay Devices; Environmental Compliance

Download Datasheet Parametric Compare View All

MDU-3C-60 Overview

Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8

MDU-3C-60 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Data Delay Devices
Parts packaging code	DIP
package instruction	DIP,
Contacts	14
Reach Compliance Code	compli
Other features	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS
series	HC/UH
Input frequency maximum value (fmax)	5.55556 MHz
JESD-30 code	R-XDIP-T8
JESD-609 code	e3
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	3
Number of taps/steps	1
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	7.747 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin (Sn)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	60 ns
width	7.62 mm

MDU-3C-60 Preview

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

MDU-3C-60 Related Products

	MDU-3C-60	MDU-3C-25	MDU-3C-30	MDU-3C-15	MDU-3C-20	MDU-3C-40	MDU-3C-50	MDU-3C-75	MDU-3C-100
Description	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8	Active Delay Line, 3-Func, 1-Tap, True Output, CMOS, DIP-14/8
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Data Delay Devices	Data Delay Devices	Data Delay Devices	Data Delay Devices	Data Delay Devices	Data Delay Devices	Data Delay Devices	Data Delay Devices	Data Delay Devices
Parts packaging code	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP
package instruction	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,
Contacts	14	14	14	14	14	14	14	14	14
Reach Compliance Code	compli	compliant	compliant	compliant	compliant	compliant	compliant	compli	compli
Other features	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS	TESTED WITH NO LOAD CONDITIONS; MIN. FAN OUT OF 10 LSTTL LOADS
series	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH
Input frequency maximum value (fmax)	5.55556 MHz	13.3333 MHz	11.1111 MHz	22.2222 MHz	16.6667 MHz	8.33333 MHz	6.66667 MHz	4.44444 MHz	3.33333 MHz
JESD-30 code	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8	R-XDIP-T8
JESD-609 code	e3	e3	e3	e3	e3	e3	e3	e3	e3
Logic integrated circuit type	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE
Number of functions	3	3	3	3	3	3	3	3	3
Number of taps/steps	1	1	1	1	1	1	1	1	1
Number of terminals	8	8	8	8	8	8	8	8	8
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
programmable delay line	NO	NO	NO	NO	NO	NO	NO	NO	NO
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	7.747 mm	7.747 mm	7.747 mm	7.747 mm	7.747 mm	7.747 mm	7.747 mm	7.747 mm	7.747 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Total delay nominal (td)	60 ns	25 ns	30 ns	15 ns	20 ns	40 ns	50 ns	75 ns	100 ns
width	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm

Recommended Resources

DC voltage stabilizing circuit and zero-crossing detection circuit in the indoor unit control circuit of Hisense KFR-25GW-06BP inverter air conditioner

Single line control indicator light circuit a

HT-1340 circuit

C523 double column vertical lathe control circuit 03

Full-bridge converter electrical schematic diagram

Computer motherboard circuit diagram 440GX_22

Zhejiang University Embedded Technology Advanced Learning Class July-August Course Schedule: Zhejiang University professional and technical trainingConsultation and registration: Teacher Qiu 0571-85622860 (daytime), 13777811228,13205718120,0571-88230155 (evening) Zhejiang University Open Cour...; shilina Embedded System

Newbie help: I just started to learn 51 recently. Can you recommend some small projects? I have a development board and want to make a small project to practice. I have learned interrupts, but I don't understand s...; 郑清源 51mcu

Single Channel Sonar Receiver - Active Butterworth Filter: [i=s] This post was last edited by bqgup on 2021-6-21 09:58 [/i] #ActiveButterworthFilter##ButterworthFilterCharacteristics The characteristic of Butterworth filter is that the frequency response curv...; bqgup Creative Market

I need advice from an expert on how to use the CXA1238S radio chip...: [i=s]This post was last edited by paulhyde on 2014-9-15 09:30[/i]I have built a radio circuit using Sony's CXA1238S, , for some reason, the FM high-frequency circuit can be adjusted to 35MHz, but the ...; komoner0 Electronics Design Contest

Newcomers report to post and earn points: Newbie reporting in, please take care of me, thank you brothers...; 静夜思狂 Talking

What is the significance of the postproc subdirectory under the release directory in PB?: Does anyone know what the release\postproc subdirectory in the PBWorkspaces project directory means? Why does it contain the same .bib and .reg configuration files as the parent directory?...; fusensam3 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components