TC55NEM208AFPN/AFTN55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 5V
±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
µA
standby current (typ) when chip enable (
CE
) is asserted high. There are two control inputs.
CE
is used to select
the device and for data retention control, and output enable (
OE
) provides fast memory access. This device is well
suited to various microprocessor system applications where high speed, low power and battery backup are required.
And, with a guaranteed operating range of
−40°
to 85°C, the TC55NEM208AFPN/AFTN can be used in
environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a
standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin
thin-small-outline package (TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V
±
10%
Power down features using
CE
.
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum):20
µA
•
Access Times (maximum):
TC55NEM208AFPN/AFTN
55
Access Time
55 ns
55 ns
30 ns
70
70 ns
70 ns
35 ns
CE
Access Time
OE
Access Time
•
Package:
SOP32-P-525-1.27 (AFPN)
(Weight:
TSOP II32-P-400-1.27 (AFTN) (Weight:
g typ)
g typ)
PIN ASSIGNMENT
(TOP VIEW)
32 PIN SOP &
TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
A17
R/W
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
PIN NAMES
A0~A18
R/W
Address Inputs
Read/Write Control
OE
CE
I/O1~I/O8
V
DD
GND
Output Enable
Chip Enable
Data Inputs/Outputs
Power (
+
5 V)
Ground
(AFPN/AFTN)
2002-09-18
1/10
TC55NEM208AFPN/AFTN55,70
BLOCK DIAGRAM
CE
A4
A5
A6
A7
A8
A9
A11
A14
A15
A16
A18
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
V
DD
GND
index
TC55NEM208AFPN/AFTN55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 5V
±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
µA
standby current (typ) when chip enable (
CE
) is asserted high. There are two control inputs.
CE
is used to select
the device and for data retention control, and output enable (
OE
) provides fast memory access. This device is well
suited to various microprocessor system applications where high speed, low power and battery backup are required.
And, with a guaranteed operating range of
−40°
to 85°C, the TC55NEM208AFPN/AFTN can be used in
environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a
standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin
thin-small-outline package (TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V
±
10%
Power down features using
CE
.
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum):20
µA
•
Access Times (maximum):
TC55NEM208AFPN/AFTN
55
Access Time
55 ns
55 ns
30 ns
70
70 ns
70 ns
35 ns
CE
Access Time
OE
Access Time
•
Package:
SOP32-P-525-1.27 (AFPN)
(Weight:
TSOP II32-P-400-1.27 (AFTN) (Weight:
g typ)
g typ)
PIN ASSIGNMENT
(TOP VIEW)
32 PIN SOP &
TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
A17
R/W
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
PIN NAMES
A0~A18
R/W
Address Inputs
Read/Write Control
OE
CE
I/O1~I/O8
V
DD
GND
Output Enable
Chip Enable
Data Inputs/Outputs
Power (
+
5 V)
Ground
(AFPN/AFTN)
2002-09-18
1/10
index
TC55NEM208AFPN/AFTN55,70
BLOCK DIAGRAM
CE
A4
A5
A6
A7
A8
A9
A11
A14
A15
A16
A18
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
V
DD
GND
MEMORY CELL ARRAY
2,048
×
256
×
8
(4,194,304)
8
DATA
CONTROL
SENSE AMP
COLUMN ADDRESS
DECODER
CLOCK
GENERATOR
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A10 A12A13 A17
OE
R/W
CE
CE
OPERATING MODE
MODE
Read
Write
Output Deselect
Standby
*
= don't care
H = logic high
L = logic low
CE
L
L
L
H
OE
L
*
R/W
H
L
H
*
I/O1~I/O8
Output
Input
High-Z
High-Z
POWER
I
DDO
I
DDO
I
DDO
I
DDS
H
*
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
−
0.3~7.0
−
0.3
*
~7.0
−
0.5~V
DD
+
0.5
UNIT
V
V
V
W
°C
°C
°C
0.6
260
−
55~150
−
40~85
*
:
−
2.0 V when measured at a pulse width of 20ns
2002-09-18
2/10
index
TC55NEM208AFPN/AFTN55,70
DC RECOMMENDED OPERATING CONDITIONS
(Ta
= −40°
to 85°C)
SYMBOL
V
DD
V
IH
V
IL
V
DH
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
MIN
4.5
2.2
−
0.3
*
TYP
5.0
MAX
5.5
V
DD
+
0.3
0.6
5.5
UNIT
V
V
V
V
2.0
*
:
−
2.0 V when measured at a pulse width of 20 ns
DC CHARACTERISTICS
(Ta
= −40°
to 85°C, V
DD
=
5 V
±
10%)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage
Current
V
IN
=
0 V~V
DD
V
OH
=
2.4 V
V
OL
=
0.4 V
TEST CONDITION
MIN
−
1.0
TYP
MAX
±
1.0
±
1.0
UNIT
µ
A
mA
mA
µ
A
2.1
CE
=
V
IH
or R/W
=
V
IL
or
OE
=
V
IH
, V
OUT
=
0 V~V
DD
CE
=
V
IL
and R/W
=
V
IH
,
I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
CE
=
0.2 V and R/W
=
V
DD
−
0.2 V,
I
OUT
=
0 mA,
Other Input
=
V
DD
−
0.2 V/0.2 V
CE
=
V
IH
Ta
=
25°C
MIN
1
µ
s
t
cycle
MIN
1
µ
s
35
mA
l
DDO1
Operating Current
l
DDO2
8
30
mA
3
I
DDS1
Standby Current
I
DDS2
3
mA
1
CE
=
V
DD
−
0.2 V,
V
DD
=
2.0 V~5.5 V
Ta
= −
40~40°C
Ta
= −
40~85°C
3
20
µ
A
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
2002-09-18
3/10
index
TC55NEM208AFPN/AFTN55,70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= −40°
to 85°C, V
DD
=
5 V
±
10%)
READ CYCLE
TC55NEM208AFPN/AFTN
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
55
55
MAX
70
MIN
70
UNIT
MAX
55
55
30
70
70
35
5
0
5
0
ns
25
25
30
30
10
10
WRITE CYCLE
TC55NEM208AFPN/AFTN
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
55
40
45
0
0
55
MAX
70
MIN
70
50
55
0
0
UNIT
MAX
ns
25
30
0
25
0
0
30
0
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
100 pF
+
1 TTL Gate
0.4 V, 2.4 V
1.5 V
1.5 V
5 ns
2002-09-18
4/10
index
TC55NEM208AFPN/AFTN55,70
TIMING DIAGRAMS
READ CYCLE
(See Note 1)
t
RC
Address
A0~A18
t
ACC
t
CO
t
OH
CE
t
OE
t
OD
OE
t
OEE
t
COE
D
OUT
I/O1~8
Hi-Z
VALID DATA OUT
Hi-Z
t
ODO
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
t
WC
Address
A0~A18
t
AS
R/W
t
CW
t
WP
t
WR
CE
t
ODW
D
OUT
I/O1~8
(See Note 2)
Hi-Z
t
DS
D
IN
I/O1~8
(See Note 5)
t
DH
(See Note 5)
t
OEW
(See Note 3)
VALID DATA IN
2002-09-18
5/10
TC55NEM208AFPN/AFTN55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 5V
±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
µA
standby current (typ) when chip enable (
CE
) is asserted high. There are two control inputs.
CE
is used to select
the device and for data retention control, and output enable (
OE
) provides fast memory access. This device is well
suited to various microprocessor system applications where high speed, low power and battery backup are required.
And, with a guaranteed operating range of
−40°
to 85°C, the TC55NEM208AFPN/AFTN can be used in
environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a
standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin
thin-small-outline package (TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V
±
10%
Power down features using
CE
.
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum):20
µA
•
Access Times (maximum):
TC55NEM208AFPN/AFTN
55
Access Time
55 ns
55 ns
30 ns
70
70 ns
70 ns
35 ns
CE
Access Time
OE
Access Time
•
Package:
SOP32-P-525-1.27 (AFPN)
(Weight:
TSOP II32-P-400-1.27 (AFTN) (Weight:
g typ)
g typ)
PIN ASSIGNMENT
(TOP VIEW)
32 PIN SOP &
TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
A17
R/W
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
PIN NAMES
A0~A18
R/W
Address Inputs
Read/Write Control
OE
CE
I/O1~I/O8
V
DD
GND
Output Enable
Chip Enable
Data Inputs/Outputs
Power (
+
5 V)
Ground
(AFPN/AFTN)
2002-09-18
1/10
TC55NEM208AFPN/AFTN55,70
BLOCK DIAGRAM
CE
A4
A5
A6
A7
A8
A9
A11
A14
A15
A16
A18
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
V
DD
GND
MEMORY CELL ARRAY
2,048
×
256
×
8
(4,194,304)
8
DATA
CONTROL
SENSE AMP
COLUMN ADDRESS
DECODER
CLOCK
GENERATOR
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A10 A12A13 A17
OE
R/W
CE
CE
OPERATING MODE
MODE
Read
Write
Output Deselect
Standby
*
= don't care
H = logic high
L = logic low
CE
L
L
L
H
OE
L
*
R/W
H
L
H
*
I/O1~I/O8
Output
Input
High-Z
High-Z
POWER
I
DDO
I
DDO
I
DDO
I
DDS
H
*
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
−
0.3~7.0
−
0.3
*
~7.0
−
0.5~V
DD
+
0.5
UNIT
V
V
V
W
°C
°C
°C
0.6
260
−
55~150
−
40~85
*
:
−
2.0 V when measured at a pulse width of 20ns
2002-09-18
2/10
TC55NEM208AFPN/AFTN55,70
DC RECOMMENDED OPERATING CONDITIONS
(Ta
= −40°
to 85°C)
SYMBOL
V
DD
V
IH
V
IL
V
DH
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
MIN
4.5
2.2
−
0.3
*
TYP
5.0
MAX
5.5
V
DD
+
0.3
0.6
5.5
UNIT
V
V
V
V
2.0
*
:
−
2.0 V when measured at a pulse width of 20 ns
DC CHARACTERISTICS
(Ta
= −40°
to 85°C, V
DD
=
5 V
±
10%)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage
Current
V
IN
=
0 V~V
DD
V
OH
=
2.4 V
V
OL
=
0.4 V
TEST CONDITION
MIN
−
1.0
TYP
MAX
±
1.0
±
1.0
UNIT
µ
A
mA
mA
µ
A
2.1
CE
=
V
IH
or R/W
=
V
IL
or
OE
=
V
IH
, V
OUT
=
0 V~V
DD
CE
=
V
IL
and R/W
=
V
IH
,
I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
CE
=
0.2 V and R/W
=
V
DD
−
0.2 V,
I
OUT
=
0 mA,
Other Input
=
V
DD
−
0.2 V/0.2 V
CE
=
V
IH
Ta
=
25°C
MIN
1
µ
s
t
cycle
MIN
1
µ
s
35
mA
l
DDO1
Operating Current
l
DDO2
8
30
mA
3
I
DDS1
Standby Current
I
DDS2
3
mA
1
CE
=
V
DD
−
0.2 V,
V
DD
=
2.0 V~5.5 V
Ta
= −
40~40°C
Ta
= −
40~85°C
3
20
µ
A
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
2002-09-18
3/10
TC55NEM208AFPN/AFTN55,70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= −40°
to 85°C, V
DD
=
5 V
±
10%)
READ CYCLE
TC55NEM208AFPN/AFTN
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
55
55
MAX
70
MIN
70
UNIT
MAX
55
55
30
70
70
35
5
0
5
0
ns
25
25
30
30
10
10
WRITE CYCLE
TC55NEM208AFPN/AFTN
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
55
40
45
0
0
55
MAX
70
MIN
70
50
55
0
0
UNIT
MAX
ns
25
30
0
25
0
0
30
0
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
100 pF
+
1 TTL Gate
0.4 V, 2.4 V
1.5 V
1.5 V
5 ns
2002-09-18
4/10
TC55NEM208AFPN/AFTN55,70
TIMING DIAGRAMS
READ CYCLE
(See Note 1)
t
RC
Address
A0~A18
t
ACC
t
CO
t
OH
CE
t
OE
t
OD
OE
t
OEE
t
COE
D
OUT
I/O1~8
Hi-Z
VALID DATA OUT
Hi-Z
t
ODO
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
t
WC
Address
A0~A18
t
AS
R/W
t
CW
t
WP
t
WR
CE
t
ODW
D
OUT
I/O1~8
(See Note 2)
Hi-Z
t
DS
D
IN
I/O1~8
(See Note 5)
t
DH
(See Note 5)
t
OEW
(See Note 3)
VALID DATA IN
2002-09-18
5/10
stm32/stm8
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