TC55NEM208AFTN70 datasheet, PDF

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TC55NEM208AFTN70: DescriptionTENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS; Categorystorage storage; File Size107KB，10 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/

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TC55NEM208AFTN70 Overview

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55NEM208AFTN70 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Toshiba Semiconductor
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP32,.46
Contacts	32
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	70 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G32
length	20.95 mm
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP32,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000003 A
Minimum standby current	2 V
Maximum slew rate	0.035 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm

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TC55NEM208AFPN/AFTN55,70

TENTATIVE

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

524,288-WORD BY 8-BIT STATIC RAM

DESCRIPTION

The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288

words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a

single 5V

10% power supply. Advanced circuit technology provides both high speed and low power at an operating

current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1

µA

standby current (typ) when chip enable (

) is asserted high. There are two control inputs.

is used to select

the device and for data retention control, and output enable (

) provides fast memory access. This device is well

suited to various microprocessor system applications where high speed, low power and battery backup are required.

And, with a guaranteed operating range of

−40°

to 85°C, the TC55NEM208AFPN/AFTN can be used in

environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a

standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin

thin-small-outline package (TSOP).

FEATURES

•

Low-power dissipation

Operating: 15 mW/MHz (typical)

Single power supply voltage of 5 V

10%

Power down features using

Data retention supply voltage of 2.0 to 5.5 V

Direct TTL compatibility for all inputs and outputs

Wide operating temperature range of

−40°

to 85°C

Standby Current (maximum):20

µA

•

Access Times (maximum):

TC55NEM208AFPN/AFTN

Access Time

55 ns

30 ns

70 ns

35 ns

Access Time

•

Package:

SOP32-P-525-1.27 (AFPN)

(Weight:

TSOP II32-P-400-1.27 (AFTN) (Weight:

g typ)

PIN ASSIGNMENT

(TOP VIEW)

32 PIN SOP &

TSOP

A18

A16

A14

A12

I/O1

I/O2

I/O3

GND

A15

A17

R/W

A13

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

PIN NAMES

A0~A18

R/W

Address Inputs

Read/Write Control

I/O1~I/O8

GND

Output Enable

Chip Enable

Data Inputs/Outputs

Power (

5 V)

Ground

(AFPN/AFTN)

2002-09-18

1/10

TC55NEM208AFTN70 Related Products

	TC55NEM208AFTN70	TC55NEM208A	TC55NEM208AFPN	TC55NEM208AFPN55	TC55NEM208AFTN	TC55NEM208AFTN55	TC55NEM208AFPN70
Description	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Is it Rohs certified?	incompatible	-	-	incompatible	-	incompatible	incompatible
Maker	Toshiba Semiconductor	-	-	Toshiba Semiconductor	-	Toshiba Semiconductor	Toshiba Semiconductor
Parts packaging code	TSOP2	-	-	SOIC	-	TSOP2	SOIC
package instruction	TSOP2, TSOP32,.46	-	-	0.525 INCH, 1.27 MM PITCH, PLASTIC, SOP-32	-	0.400 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-32	SOP, SOP32,.56
Contacts	32	-	-	32	-	32	32
Reach Compliance Code	unknow	-	-	unknow	-	unknow	unknow
Maximum access time	70 ns	-	-	55 ns	-	55 ns	70 ns
JESD-30 code	R-PDSO-G32	-	-	R-PDSO-G32	-	R-PDSO-G32	R-PDSO-G32
length	20.95 mm	-	-	20.6 mm	-	20.95 mm	20.6 mm
memory density	4194304 bi	-	-	4194304 bi	-	4194304 bi	4194304 bi
Memory IC Type	STANDARD SRAM	-	-	STANDARD SRAM	-	STANDARD SRAM	STANDARD SRAM
memory width	8	-	-	8	-	8	8
Number of functions	1	-	-	1	-	1	1
Number of terminals	32	-	-	32	-	32	32
word count	524288 words	-	-	524288 words	-	524288 words	524288 words
character code	512000	-	-	512000	-	512000	512000
Operating mode	ASYNCHRONOUS	-	-	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	-	-	85 °C	-	85 °C	85 °C
Minimum operating temperature	-40 °C	-	-	-40 °C	-	-40 °C	-40 °C
organize	512KX8	-	-	512KX8	-	512KX8	512KX8
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	-	-	SOP	-	TSOP2	SOP
Package shape	RECTANGULAR	-	-	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	-	-	SMALL OUTLINE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE
Parallel/Serial	PARALLEL	-	-	PARALLEL	-	PARALLEL	PARALLEL
Certification status	Not Qualified	-	-	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	-	-	2.8 mm	-	1.2 mm	2.8 mm
Maximum supply voltage (Vsup)	5.5 V	-	-	5.5 V	-	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	-	-	4.5 V	-	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	-	-	5 V	-	5 V	5 V
surface mount	YES	-	-	YES	-	YES	YES
technology	CMOS	-	-	CMOS	-	CMOS	CMOS
Temperature level	INDUSTRIAL	-	-	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	-	-	GULL WING	-	GULL WING	GULL WING
Terminal pitch	1.27 mm	-	-	1.27 mm	-	1.27 mm	1.27 mm
Terminal location	DUAL	-	-	DUAL	-	DUAL	DUAL
width	10.16 mm	-	-	10.7 mm	-	10.16 mm	10.7 mm

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