Preliminary
GS81302R19/37E-400/375
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
144Mb SigmaCIO DDR-II+
Burst of 4 SRAM
400 MHz–375 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaCIO™ Family Overview
The GS81302R19/37E are built in compliance with the
SigmaCIO DDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302R19/37E SigmaCIO SRAMs are just
one element in a family of low power, low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302R19/37E SigmaCIO DDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Common I/O SigmaCIO DDR-II+ B4 RAMs always transfer
data in four packets. When a new address is loaded, A0 and A1
preset an internal 2 bit linear address counter. The counter
increments by 1 for each beat of a burst of four data transfer.
The counter always wraps to 00 after reaching 11, no matter
where it starts.
Rev: 1.00 10/2007
1/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302R19/37E-400/375
4M x 36 SigmaCIO DDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
7
BW1
BW0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC/SA
(288Mb)
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
2. NC = Not connected
Rev: 1.00 10/2007
2/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302R19/37E-400/375
8M x 18 SigmaCIO DDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
7
SA
BW0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
2. NC = Not connected
Rev: 1.00 10/2007
3/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302R19/37E-400/375
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW3
LD
K
K
TMS
TDI
TCK
TDO
V
REF
ZQ
MCL
DQ
Doff
CQ
CQ
V
DD
V
DDQ
V
SS
QVLD
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Synchronous Load Pin
Input Clock
Input Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Must Connect Low
Data I/O
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Q Valid Output
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Input/Output
Input
Output
Output
Supply
Supply
Supply
Output
Comments
—
—
Active High
Active Low
Active Low
x18/x36 only
Active Low
Active High
Active Low
—
—
—
—
—
—
—
Three State
Active Low
—
—
1.8 V Nominal
1.5 V Nominal
—
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
Rev: 1.00 10/2007
4/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302R19/37E-400/375
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs
are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated
in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is
possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are
inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from
loading read or write command
inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.
SigmaCIO DDR-II B4 SRAM Read Cycles
The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in
response to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins
are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined
reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces
data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data
is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of
four transfers per address load.
SigmaCIO DDR-II B4 SRAM Write Cycles
The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/
W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is
checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the
rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst
of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the
next rising edge of K#, for a total of four transfers per address load.
Rev: 1.00 10/2007
5/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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