1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
Rev 1.0, November 25, 2006
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Page 1 of 17
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CY28339
Pin Definitions
Pin Number
47
1
2
43, 42,
39, 38
29
31
20
17, 18, 19
6
REF0
XIN
XOUT
CPUT1,CPUC1
CPUT2, CPUC2
3V66_0
3V66_1/VCH
66IN/3V66_5
66BUFF [2:0] /3V66
[4:2]
PCIF
Name
I/O
3.3V 14.318 MHz clock output.
14.318 MHz crystal input.
14.318 MHz crystal input.
Differential CPU clock outputs.
3.3V 66 MHz clock output.
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal
VCO.
66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO.
33 MHz clocks divided down from 66Input or divided down from 3V66;
PCIF
default is free-running.
PCI clock outputs divided down from 66Input or divided down from 3V66;
PCI [7:8] are configurable as free-running PCI through SMBus.
[2]
Fixed 48 MHz clock output.
Fixed 48 MHz clock output.
Special 3.3V three-level input for Mode selection.
3.3V LVTTL inputs for CPU frequency selection.
A precision resistor is attached to this pin which is connected to the internal
current reference.
3.3V LVTTL input for Power_Down# (active LOW).
3.3V LVTTL input for PCI_STOP# (active LOW).
3.3V LVTTL input for CPU_STOP# (active LOW).
3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1]
inputs are valid and OK to be sampled (Active LOW).
Once VTT_PWRGD#
is sampled LOW, the status of this input will be ignored.
SMBus-compatible SDATA.
SMBus-compatible SCLK.
3.3V power supply for outputs.
Description
8, 9, 10, 12, 13, 14, PCI [0:2]
4, 5
PCI [4:6]
PCI [7:8]
35
34
36
46
37
21
30
45
24
USB_48M
DOT_48M
S2
S1
IREF
PD#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
25
26
SDATA
SCLK
11, 15, 28, 40, 44, VDD_PCI,
48
VDD_3V66,
VDD_CPU,VDD_REF
33
22
VDD_48 MHz
VDD_CORE
3.3V power supply for 48 MHz.
3.3V power supply for phase-locked loop (PLL).
Ground for outputs.
3, 7, 16, 27, 32, 41 GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
GND_CPU
23
GND_CORE
Note:
2. PCI3 is internally disabled and is not accessible.
Ground for PLL.
Rev 1.0, November 25, 2006
Page 2 of 17
CY28339
Two-Wire SMBus Control Interface
The two-wire control interface implements a Read/Write slave
only interface according to SMBus specification.
The device will accept data written to the D2 address and data
may read back from address D3. It will not respond to any
other addresses, and previously set control registers are
retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1. “Command code“ byte
2. “Byte count” byte.
Although the data (bits) in the command is considered “don’t
care,” it must be sent and will be acknowledged. After the
Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Byte 0: CPU Clock Register
[3,4]
Bit
7
6
@Pup
0
0
Name
Description
Spread Spectrum Enable.
0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
CPU Clock Power-down Mode Select.
0 = Drive CPUT to 2x IREF and drive CPUC LOW
1 = Tri-state all CPU outputs.
This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#.
3V66_1/VCH 3V66_1/VCH Frequency Select
0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit.
Reserved
HW
HW
HW
1
PCI_STOP# Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP#
is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin.
S2
S1
Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only.
Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only.
Reserved
5
4
3
2
1
0
0
Byte 1: CPU Clock Register
Bit
7
6
@Pup
1
0
Name
Reserved
CPUT1, CPUC1 CPUT/C Output Functionality Control when CPU_STOP# is asserted.
CPUT2, CPUC2 0 = Drive CPUT to 6x IREF and drive CPUC LOW
1 = three-state all CPU outputs.
This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs
will be three-stated.
CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted.
0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit.
CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted.
0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit.
Reserved
CPUT2, CPUC2 CPUT/C2 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
CPUT1, CPUC1 CPUT/C1 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
Reserved
Description
5
4
3
2
1
0
0
0
0
1
1
1
Notes:
3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.
4. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.
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