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LTC2216IUP#TR

Description
IC 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64, 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64, Analog to Digital Converter
CategoryAnalog mixed-signal IC    converter   
File Size2MB,36 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric View All

LTC2216IUP#TR Overview

IC 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64, 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64, Analog to Digital Converter

LTC2216IUP#TR Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC64,.35SQ,20
Contacts64
Reach Compliance Code_compli
ECCN code3A001.A.5.A.5
Maximum analog input voltage2.75 V
Minimum analog input voltage
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N64
JESD-609 codee0
length9 mm
Maximum linear error (EL)0.0053%
Humidity sensitivity level1
Number of analog input channels1
Number of digits16
Number of functions1
Number of terminals64
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC64,.35SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)235
power supply3.3 V
Certification statusNot Qualified
Sampling rate80 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width9 mm
FEATURES
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n
LTC2216/LTC2215
16-Bit, 80Msps/65Msps
Low Noise ADC
DESCRIPTION
The LTC
®
2216/LTC2215 are 80Msps/65Msps sampling 16-
bit A/D converters designed for digitizing high frequency,
wide dynamic range signals with input frequencies up to
400MHz. The input range of the ADC is fixed at 2.75V
P-P
.
The LTC2216/LTC2215 are perfect for demanding com-
munications applications, with AC performance that
includes 81.5dBFS noise floor and 100dB spurious free
dynamic range (SFDR). Ultra low jitter of 85fs
RMS
allows
undersampling of high input frequencies while maintaining
excellent noise performance. Maximum DC specs include
±3.5LSB INL, ±1LSB DNL (no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Sample Rate: 80Msps/65Msps
81.5dBFS Noise Floor
100dB SFDR
SFDR >95dB at 70MHz
85fs
RMS
Jitter
2.75V
P-P
Input Range
400MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 970mW/700mW
Clock Duty Cycle Stabilizer
Pin-Compatible with LTC2208, LTC2217
64-Pin (9mm
×
9mm) QFN Package
APPLICATIONS
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n
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATION
3.3V
SENSE
V
CM
2.2μF
1.575V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
OV
DD
0.5V TO 3.6V
1μF
OF
CLKOUT
D15
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
V
DD
GND
ENC
+
ENC
SHDN
DITH
MODE
LVDS
RAND
1μF
1μF
3.3V
1μF
22165 TA01
LTC2216: 64k Point FFT,
f
IN
= 4.9MHz, –1dBFS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
20
30
FREQUENCY (MHz)
40
22165 TA01b
ANALOG
INPUT
AIN
S/H
AMP
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
CMOS
OR
LVDS
ADC CONTROL INPUTS
AMPLITUDE (dBFS)
AIN
+
+
22165f
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