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SYS32256LKL-35

Description
SRAM Module, 256KX32, 35ns, CMOS, PLASTIC, SIMM-64
Categorystorage    storage   
File Size115KB,7 Pages
ManufacturerMOSA
Websitehttp://www.mosanalog.com
Download Datasheet Parametric View All

SYS32256LKL-35 Overview

SRAM Module, 256KX32, 35ns, CMOS, PLASTIC, SIMM-64

SYS32256LKL-35 Parametric

Parameter NameAttribute value
MakerMOSA
Parts packaging codeSIMM
package instruction,
Contacts64
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time35 ns
JESD-30 codeR-XSMA-N64
memory density8388608 bi
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals64
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX32
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationSINGLE
256K x 32 SRAM MODULE
SYS32256ZK/LK - 020/25/30/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.7 : January 1999
Description
The SYS32256 is a plastic 8M Static RAM Module
offered in 64 pin ZIP and 64 lead SIMM package,
organised as 256K x 32. The module utilises eight
very fast SRAMs housed in SOJ packages, and
uses double sided surface mount techniques, to
achieve a very high density module.
Four chip selects are used to independently enable
the four bytes. Reading or Writing is executed on
individual or any combination of multiple bytes. Two
pins PD0 & PD1 are used to identify module
memory density where alternative versions of the
JEDEC standard modules can be interchanged.
Features
Access Times of 020/25/30/35 ns.
64 Pin ZIP & SIMM JEDEC standard pinouts.
5 Volt Supply ± 10%.
Power Dissipation 35ns:
Operating (32bit mode)
6.60 W (maximum).
Standby (CMOS) -L
4.40 mW (maximum).
Completely Static Operation.
Equal Access and Cycle Times.
All Inputs and Outputs Directly TTL Compatible.
On-board Supply Decoupling Capacitors.
Block Diagram
A0-A17
OE
WE
256k
x4
CS1
256k
x4
CS2
256k
x4
CS3
256k
x4
CS4
D24-D27
256k
x4
D28-D31
D16-D19
256k
x4
D20-D23
D8-D11
256k
x4
D12-D15
D0-D3
256k
x4
D4-D7
Pin Definition
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
PD1
D8
D9
D10
D11
A0
A1
A2
D12
D13
D14
D15
GND
A15
CS2
CS4
A17
OE
D24
D25
D26
D27
A3
A4
A5
VCC
A6
D28
D29
D30
D31
PD0
D0
D1
D2
D3
VCC
A7
A8
A9
D4
D5
D6
D7
WE
A14
CS1
CS3
A16
GND
D16
D17
D18
D19
A10
A11
A12
A13
D20
D21
D22
D23
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Pin Functions
Address Inputs
Data Input/Output
Chip Select Input
Read/Write Input
Output Enable Input
Power (+5V)
Ground
A0 - A17
D0 - D31
CS1- CS4
WE
OE
V
CC
GND
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