D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
5 V, Slew-Rate Limited, Half-Duplex and
Full-Duplex RS-485/RS-422 Transceivers
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 µA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC, LFCSP, and MSOP packages
FUNCTIONAL BLOCK DIAGRAMS
V
CC
ADM4850/ADM4851/
ADM4852/ADM4853
RO
RE
DE
DI
D
04931-001
R
A
B
GND
Figure 1.
V
CC
ADM4854/ADM4855/
ADM4856/ADM4857
A
RO
R
B
Z
DI
D
Y
04931-028
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
GND
Figure 2.
GENERAL DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication on
multipoint bus transmission lines. They are designed for balanced
data transmission and comply with EIA Standards RS-485 and
RS-422. The ADM4850/ADM4851/ADM4852/ADM4853 are half-
duplex transceivers that share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854/ADM4855/ADM4856/ADM4857 transceivers have
dedicated differential line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Because only one driver
should be enabled at any time, the output of a disabled or pow-
ered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures
a logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC, LFCSP
(ADM4850/ADM4851/ADM4852/ADM4853), and MSOP
(ADM4850 only) packages.
Table 1. Selection Table
Part No.
ADM4850
ADM4851
ADM4852
ADM4853
ADM4854
ADM4855
ADM4856
ADM4857
Half-/Full-Duplex
Half
Half
Half
Half
Full
Full
Full
Full
Data Rate
115 kbps
500 kbps
2.5 Mbps
10 Mbps
115 kbps
500 kbps
2.5 Mbps
10 Mbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADM4850/ADM4854 Timing Specifications ........................... 4
ADM4851/ADM4855 Timing Specifications ........................... 4
ADM4852/ADM4856 Timing Specifications ........................... 5
ADM4853/ADM4857 Timing Specifications ........................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 10
Switching Characteristics .............................................................. 11
Circuit Description......................................................................... 12
Slew-Rate Control ...................................................................... 12
Receiver Input Filtering ............................................................. 12
Half-/Full-Duplex Operation ................................................... 12
High Receiver Input Impedance .............................................. 13
Three-State Bus Connection ..................................................... 13
Shutdown Mode ......................................................................... 13
Fail-Safe Operation .................................................................... 13
Current Limit and Thermal Shutdown ................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
1/11—Rev. B to Rev. C
Change to Table 8, Pin 3 Description ............................................ 7
Changes to Figure 29 ...................................................................... 12
Changes to Ordering Guide .......................................................... 15
7/09—Rev. A to Rev. B
Added MSOP Package .................................................. Throughout
Changes to Table 2 ............................................................................ 3
Changes to Table 7 ............................................................................ 6
Added Figure 4; Renumbered Figures Sequentially..................... 7
Moved Typical Performance Characteristics Section .................. 8
Changes to Figure 24, Figure 27 ................................................... 11
Changes to Figure 29 ...................................................................... 12
Change to Shutdown Mode Section ............................................. 13
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 15
10/04—Revision 0: Initial Version
Rev. C | Page 2 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
SPECIFICATIONS
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DRIVER
Differential Output Voltage, V
OD
Min
Typ
Max
V
CC
5
5
5
0.2
3
0.2
+200
+200
0.8
2.0
±1
220
−200
96
−125
20
150
−30
Unit
V
V
V
V
V
V
V
mA
mA
V
V
µA
kΩ
mV
mV
kΩ
mA
mA
µA
V
V
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
−7 V < V
OC
< +12 V
−7 V < V
OC
< +12 V
−7 V < V
OC
< +12 V
V
IN
= +12 V
V
IN
= −7 V
I
OUT
= +4 mA
I
OUT
= −4 mA
V
OUT
= GND or V
CC
0.4 V ≤ V
OUT
≤ 2.4 V
DE = 0 V, RE = V
CC
(shutdown)
DE = 0 V, RE = 0 V
DE = V
CC
DE = 0 V, RE = V
CC
(shutdown)
DE = 0 V, RE = 0 V
DE = V
CC
DE = 0 V, RE = V
CC
(shutdown)
DE = 0 V, RE = 0 V
DE = V
CC
DE = 0 V, RE = V
CC
(shutdown)
DE = 0 V, RE = 0 V
DE = V
CC
Test Conditions/Comments
R = ∞, see Figure 18
1
R = 50 Ω (RS-422), see Figure 18
R = 27 Ω (RS-485), see Figure 18
V
TST
= −7 V to 12 V, see Figure 19
R = 27 Ω or 50 Ω, see Figure 18
R = 27 Ω or 50 Ω, see Figure 18
R = 27 Ω or 50 Ω, see Figure 18
−7 V < V
OUT
< +12 V
−7 V < V
OUT
< +12 V
|V
OD3
|
∆|V
OD
| for Complementary Output States
Common-Mode Output Voltage, V
OC
∆|V
OC
| for Complementary Output States
Output Short-Circuit Current, V
OUT
= High
Output Short-Circuit Current, V
OUT
= Low
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low
CMOS Input Logic Threshold High
CMOS Logic Input Current (DI)
DE Input Resistance to GND
RECEIVER
Differential Input Threshold Voltage, V
TH
Input Hysteresis
Input Resistance (A, B)
Input Current (A, B)
CMOS Logic Input Current (RE)
CMOS Output Voltage Low
CMOS Output Voltage High
Output Short-Circuit Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
115 kbps Options (ADM4850/ADM4854)
2.0
1.5
1.5
−200
−200
0.125
−0.1
±1
0.4
4.0
7
85
±2
5
60
160
5
120
200
5
400
500
5
400
500
36
100
500 kbps Options (ADM4851/ADM4855)
80
120
2.5 Mbps Options (ADM4852/ADM4856)
250
320
10 Mbps Options (ADM4853/ADM4857)
250
320
1
Guaranteed by design.
Rev. C | Page 3 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, t
PLH
, t
PHL
Skew, t
SKEW
Rise/Fall Times, t
R
, t
F
Enable Time, t
ZH
Disable Time, t
ZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, t
PLH
, t
PHL
Differential Skew, t
SKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
1
Min
115
600
600
Typ
Max
Unit
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
2500
70
2400
2000
2000
4000
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 20
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 20
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 20
R
L
= 500 Ω, C
L
= 100 pF, see Figure 21, ADM4850
R
L
= 500 Ω, C
L
= 15 pF, see Figure 21, ADM4850
R
L
= 500 Ω, C
L
= 100 pF, see Figure 21, ADM4850
C
L
= 15 pF, see Figure 22
C
L
= 15 pF, see Figure 22
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 23, ADM4850
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 23, ADM4850
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 23, ADM4850
ADM4850
1
400
5
20
4000
330
1000
255
50
50
3000
50
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, t
PLH
, t
PHL
Skew, t
SKEW
Rise/Fall Times, t
R
, t
F
Enable Time, t
ZH
Disable Time, t
ZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, t
PLH
, t
PHL
Differential Skew, t
SKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
1
Min
500
250
200
Typ
Max
Unit
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
600
40
600
1000
1000
4000
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 20
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 20
R
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 20
R
L
= 500 Ω, C
L
= 100 pF, see Figure 21, ADM4851
R
L
= 500 Ω, C
L
= 15 pF, see Figure 21, ADM4851
R
L
= 500 Ω, C
L
= 100 pF, see Figure 21, ADM4851
C
L
= 15 pF, see Figure 22
C
L
= 15 pF, see Figure 22
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 23, ADM4851
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 23, ADM4851
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 23, ADM4851
ADM4851
1
400
5
20
4000
330
1000
250
50
50
3000
50
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. C | Page 4 of 16
Wireless Connectivity
京公网安备 11010802033920号
EEWORLD
