SA24C1024 Datasheet
SAIFUN
2
General Description
The SA24C1024 is a 1024Kbit CMOS non-
volatile serial EEPROM organized as 128K
x 8 bit memory. This device conforms to
Extended IIC 2-wire protocol, which
enables accessing of memory in excess of
16 Kbits on an IIC bus. This serial
communication protocol uses a Clock
signal (SCL) and a Data signal (SDA) to
synchronously clock data between a
Master (for example, a microcontroller) and
a Slave (EEPROM).
The SA24C1024 offers hardware write
protection whereby the entire memory
array can be write-protected by pulling the
WP pin to logic HIGH. The entire memory
then becomes unalterable until the WP pin
is switched to logic LOW. The device also
features programmable write protect with
options of full, half or a quadrant of the
array.
The LZ version of the SA24C1024 offers
very low standby current, which makes it
suitable for low power applications. The
SA24C1024 is designed to minimize pin
count and simplify PC board layout
requirements. This device is offered in both
SO and DIP packages. A leadless
microleadframe package and CSP are
under development.
Saifun’s EEPROMs are designed and
tested for applications requiring high
endurance, high reliability and low power
consumption.
SA24C1024 Datasheet
SAIFUN
3
Table of Contents
Features ......................................................................... 1
General Description ...................................................... 2
Block Diagram ............................................................... 4
Connection Diagrams ................................................... 5
Ordering Information .................................................... 6
Product Specifications ................................................. 7
Absolute Maximum Ratings Operating Conditions... 7
ESD/Latch up Specification (JEDEC 8 Spec) ........... 7
Operating Conditions............................................... 7
V
CC
(2.7 V to 3.6 V) DC Electrical Characteristics ... 8
Capacitance ............................................................ 8
AC Test Conditions ................................................. 9
AC Testing Input/Output Waveforms....................... 9
AC Characteristics (V
CC
2.7 V – 3.6 V).................... 9
Bus Timing ............................................................ 10
Write Cycle Timing ................................................ 11
Typical System Configuration................................ 11
Background Information (IIC Bus) ............................. 12
Slave Address ....................................................... 12
Device Type .......................................................... 13
Device/Page Block Selection................................. 13
Read/Write Bit....................................................... 13
Acknowledge......................................................... 13
Array Address#1.................................................... 13
Array Address#0.................................................... 13
Pin Descriptions.......................................................... 14
Serial Clock (SCL)................................................. 14
Serial Data (SDA).................................................. 14
Write Protect (WP) ................................................ 14
Choice 1: Full Array Write Protect ................. 14
Device Selection Input – A1 (as Appropriate) ........ 14
Choice 2: Programmable Write Protect ......... 15
Device Operation......................................................... 16
Clock and Data Conventions ................................. 16
START Condition .................................................. 16
STOP Condition .................................................... 16
SA24C1024 Array Addressing............................... 16
Write Operations ......................................................... 18
Byte Write ............................................................. 18
Page Write ............................................................ 18
Acknowledge Polling ............................................. 19
Write Protection .................................................... 19
Read Operations ......................................................... 20
Current Address Read........................................... 20
Random Read ....................................................... 20
Sequential Read.................................................... 20
Switching from Standard/Fast Modes to High-speed
Mode and Back ....................................................... 22
Physical Dimensions................................................... 24
Contact Information .................................................... 27
Life Support Policy...................................................... 27
List of Figures
Figure 1. SA24C1024 Block Diagram .............................. 4
Figure 2. SO Package (MW), Dual Inline (N) – Top View 5
Figure 3. Leadless Package (MLF) – Top View ............... 5
Figure 4. SA24C1024 Ordering Information..................... 6
Figure 5. AC Testing Input/Output Waveforms ................ 9
Figure 6. Bus Timing ..................................................... 10
Figure 7. Write Cycle Timing ......................................... 11
Figure 8. Typical System Configuration ......................... 11
Figure 9. Slave Address ................................................ 12
Figure 10. Data Validity ................................................. 17
Figure 11. START and STOP Definition ........................ 17
Figure 12. Acknowledge Response from Receiver ........ 17
Figure 13. Byte Write .................................................... 19
Figure 14. Page Write ................................................... 19
Figure 15. Current Address Read.................................. 21
Figure 16. Random Read .............................................. 21
Figure 17. Sequential Read........................................... 21
Figure 18. Data Transfer ............................................... 22
Figure 19. A Complete HS Mode Transfer..................... 23
Figure 20. 8-pin Molded Small Outline Package (MW8),
Package Number M08D ...................................... 24
Figure 21. Molded Dual-in-Line Package (N), Package
Number N08E...................................................... 25
Figure 22. 8-pin MLF Leadless Package ....................... 26
List of Tables
Table 1. Pin Names......................................................... 5
Table 2. Write Protection Truth Table............................ 14
SA24C1024 Datasheet
SAIFUN
5
Connection Diagrams
NC
A1
NC
V
SS
1
2
SA24C1024
3
4
6
5
SCL
SDA
NC
V
SS
3
4
8
7
V
CC
WP
NC
A1
1
2
SA24C1024
8
7
6
5
V
CC
SCL
SDA
Figure 2. SO Package (MW), Dual Inline (N) – Top
View
Figure 3. Leadless Package (MLF) – Top View
Note:
For more details, refer to package number N08E and M08D.
Table 1. Pin Names
Symbol
NC
A1
NC
V
SS
SDA
SCL
Pin Name
Not Connected
Device Select Address Input
Pin
Not Connected
Device Ground Input Pin
IIC Data Input/Output Pin
IIC Clock Input Pin
Description
Has an internal "weak" pulldown, and assumes logic LOW
when left unconnected.
Open Collector/Drain type.
Has an internal "weak" pulldown, and assumes logic LOW
when left unconnected.
WP
Write Protect
When LOW, writing is allowed to the memory array.
When HIGH, writing is not allowed to the memory array, as
defined in
Write Protect (WP),
page 14.
V
CC
Device Power Input Pin
2.7 V to 3.6 V
Note:
No A2 or A0 pins (Pins 2 and 3) are provided, and are instead treated as Not
Connected. Internal address comparison assumes pin A2 to be 0, and so the
command code should have its corresponding A2 bit set to 0 as well. The
command code should also have its corresponding A0 bit set to add16 (MSB
address bit).
FPGA/CPLD
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